[llvm] [AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (PR #140694)

[Shilei Tian via llvm-commits]

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@@ -12996,6 +13020,48 @@ SDValue SITargetLowering::performOrCombine(SDNode *N,
     }
   }
 
+  // Detect identity v2i32 OR and replace with identity source node.
+  // Specifically an Or that has operands constructed from the same source node
+  // via extract_vector_elt and build_vector. I.E.
+  // v2i32 or(
+  //   v2i32 build_vector(
+  //     i32 extract_elt(%IdentitySrc, 0),
+  //     i32 0
+  //   ),
+  //   v2i32 build_vector(
+  //     i32 0,
+  //     i32 extract_elt(%IdentitySrc, 1)
+  //   ) )
+  // =>
+  // v2i32 %IdentitySrc
+
+  if (VT == MVT::v2i32 && LHS->getOpcode() == ISD::BUILD_VECTOR &&
+      RHS->getOpcode() == ISD::BUILD_VECTOR) {
+
+    if (auto *LC = dyn_cast<ConstantSDNode>(LHS->getOperand(1)))
+      if (auto *RC = dyn_cast<ConstantSDNode>(RHS->getOperand(0))) {
+
+        // Test for and normalise build vectors.
+        if (LC->getZExtValue() == 0 && RC->getZExtValue() == 0) {
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shiltian wrote:

I'd write this part like following to avoid massive indentation:

```
auto *LC = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
auto *RC = dyn_cast<ConstantSDNode>(RHS->getOperand(0))
if (LC && RC && LC->getZExtValue() == 0 && RC->getZExtValue() == 0) {
  ...
}

https://github.com/llvm/llvm-project/pull/140694