[llvm] [RISCV] Update SpacemiT X60 scheduling latencies based on hardware measurements (PR #144730)

[Mikhail R. Gadelha via llvm-commits]

https://github.com/mikhailramalho created https://github.com/llvm/llvm-project/pull/144730

This patch updates the RISC-V SpacemiT X60 scheduling model with latency values collected from the X60 hardware. The previous values were empirically derived but were slightly off.

  Changes:
  - LoadLatency (baseline for load instructions): 5 --> 3 cycles
  - Memory operations: unified at 4 cycles
  - Atomic loads/stores: 5 --> 8 cycles
  - Atomic RMW operations: 5 --> 12 cycles

Hardware-measured values provide more accurate instruction scheduling for the in-order X60 core. Testing shows NFC across benchmarks except for 523.xalancbmk_r (known to be noisy).

https://lnt.lukelau.me/db_default/v4/nts/663?compare_to=657

>From 715b4a4859dcba615315fb4a7a321a221105388e Mon Sep 17 00:00:00 2001
From: "Mikhail R. Gadelha" <mikhail at igalia.com>
Date: Mon, 16 Jun 2025 11:48:50 -0300
Subject: [PATCH 1/2] Update latency for load and store instructions

Signed-off-by: Mikhail R. Gadelha <mikhail at igalia.com>
---
 llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
index 8948694c420a0..92835f12007d7 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
@@ -16,7 +16,7 @@
 def SpacemitX60Model : SchedMachineModel {
   let IssueWidth        = 2; // dual-issue
   let MicroOpBufferSize = 0; // in-order
-  let LoadLatency       = 5; // worse case: >= 3
+  let LoadLatency       = 3; // worse case: >= 3
   let MispredictPenalty = 9; // nine-stage
 
   let CompleteModel = 0;
@@ -114,7 +114,7 @@ def : WriteRes<WriteBEXT, [SMX60_IEU]>;
 def : WriteRes<WriteBEXTI, [SMX60_IEU]>;
 
 // Memory/Atomic memory
-let Latency = 3 in {
+let Latency = 4 in {
   def : WriteRes<WriteSTB, [SMX60_LS]>;
   def : WriteRes<WriteSTH, [SMX60_LS]>;
   def : WriteRes<WriteSTW, [SMX60_LS]>;
@@ -122,11 +122,7 @@ let Latency = 3 in {
   def : WriteRes<WriteFST16, [SMX60_LS]>;
   def : WriteRes<WriteFST32, [SMX60_LS]>;
   def : WriteRes<WriteFST64, [SMX60_LS]>;
-  def : WriteRes<WriteAtomicSTW, [SMX60_LS]>;
-  def : WriteRes<WriteAtomicSTD, [SMX60_LS]>;
-}
 
-let Latency = 5 in {
   def : WriteRes<WriteLDB, [SMX60_LS]>;
   def : WriteRes<WriteLDH, [SMX60_LS]>;
   def : WriteRes<WriteLDW, [SMX60_LS]>;
@@ -137,9 +133,14 @@ let Latency = 5 in {
 }
 
 // Atomics
-let Latency = 5 in {
+let Latency = 9 in {
+  def : WriteRes<WriteAtomicSTW, [SMX60_LS]>;
+  def : WriteRes<WriteAtomicSTD, [SMX60_LS]>;
   def : WriteRes<WriteAtomicLDW, [SMX60_LS]>;
   def : WriteRes<WriteAtomicLDD, [SMX60_LS]>;
+}
+
+let Latency = 13 in {
   def : WriteRes<WriteAtomicW, [SMX60_LS]>;
   def : WriteRes<WriteAtomicD, [SMX60_LS]>;
 }

>From 9ac6f7b42b222a53e2e9c5fa30439242b0e41507 Mon Sep 17 00:00:00 2001
From: "Mikhail R. Gadelha" <mikhail at igalia.com>
Date: Tue, 17 Jun 2025 10:50:42 -0300
Subject: [PATCH 2/2] Reduce it slightly

Signed-off-by: Mikhail R. Gadelha <mikhail at igalia.com>
---
 llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
index 92835f12007d7..9059d5a4e497b 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
@@ -133,14 +133,14 @@ let Latency = 4 in {
 }
 
 // Atomics
-let Latency = 9 in {
+let Latency = 8 in {
   def : WriteRes<WriteAtomicSTW, [SMX60_LS]>;
   def : WriteRes<WriteAtomicSTD, [SMX60_LS]>;
   def : WriteRes<WriteAtomicLDW, [SMX60_LS]>;
   def : WriteRes<WriteAtomicLDD, [SMX60_LS]>;
 }
 
-let Latency = 13 in {
+let Latency = 12 in {
   def : WriteRes<WriteAtomicW, [SMX60_LS]>;
   def : WriteRes<WriteAtomicD, [SMX60_LS]>;
 }