[llvm] ARM: Move ABI enum from TargetMachine to TargetParser (PR #144725)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 18 08:22:25 PDT 2025
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/144725
None
>From 9476487907bafa0235ad849680e23e5ac6b00e29 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 19 Jun 2025 00:14:43 +0900
Subject: [PATCH] ARM: Move ABI enum from TargetMachine to TargetParser
---
.../llvm/TargetParser/ARMTargetParser.h | 10 ++++++
llvm/lib/Target/ARM/ARMSubtarget.cpp | 14 ++++----
llvm/lib/Target/ARM/ARMTargetMachine.cpp | 35 +++++--------------
llvm/lib/Target/ARM/ARMTargetMachine.h | 11 ++----
llvm/lib/Target/ARM/ARMTargetObjectFile.cpp | 2 +-
llvm/lib/TargetParser/ARMTargetParser.cpp | 17 +++++++++
6 files changed, 46 insertions(+), 43 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.h b/llvm/include/llvm/TargetParser/ARMTargetParser.h
index 798c578ced938..3ae6c4956656d 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.h
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.h
@@ -27,6 +27,13 @@ class Triple;
namespace ARM {
+enum ARMABI {
+ ARM_ABI_UNKNOWN,
+ ARM_ABI_APCS,
+ ARM_ABI_AAPCS, // ARM EABI
+ ARM_ABI_AAPCS16
+};
+
// Arch extension modifiers for CPUs.
// Note that this is not the same as the AArch64 list
enum ArchExtKind : uint64_t {
@@ -265,6 +272,9 @@ LLVM_ABI unsigned parseArchVersion(StringRef Arch);
LLVM_ABI void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values);
LLVM_ABI StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU);
+LLVM_ABI ARMABI computeTargetABI(const Triple &TT, StringRef CPU,
+ StringRef ABIName = "");
+
/// Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
///
/// \param Arch the architecture name (e.g., "armv7s"). If it is an empty
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 91d385a0b5950..2b66ebde2dcec 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -323,17 +323,17 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
bool ARMSubtarget::isTargetHardFloat() const { return TM.isTargetHardFloat(); }
bool ARMSubtarget::isAPCS_ABI() const {
- assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
- return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
+ assert(TM.TargetABI != ARM::ARM_ABI_UNKNOWN);
+ return TM.TargetABI == ARM::ARM_ABI_APCS;
}
bool ARMSubtarget::isAAPCS_ABI() const {
- assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
- return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
- TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
+ assert(TM.TargetABI != ARM::ARM_ABI_UNKNOWN);
+ return TM.TargetABI == ARM::ARM_ABI_AAPCS ||
+ TM.TargetABI == ARM::ARM_ABI_AAPCS16;
}
bool ARMSubtarget::isAAPCS16_ABI() const {
- assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
- return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
+ assert(TM.TargetABI != ARM::ARM_ABI_UNKNOWN);
+ return TM.TargetABI == ARM::ARM_ABI_AAPCS16;
}
bool ARMSubtarget::isROPI() const {
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index fee77a44e5e80..c66232ef4dc7a 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -121,29 +121,10 @@ static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
return std::make_unique<ARMElfTargetObjectFile>();
}
-static ARMBaseTargetMachine::ARMABI
-computeTargetABI(const Triple &TT, StringRef CPU,
- const TargetOptions &Options) {
- StringRef ABIName = Options.MCOptions.getABIName();
-
- if (ABIName.empty())
- ABIName = ARM::computeDefaultTargetABI(TT, CPU);
-
- if (ABIName == "aapcs16")
- return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
- else if (ABIName.starts_with("aapcs"))
- return ARMBaseTargetMachine::ARM_ABI_AAPCS;
- else if (ABIName.starts_with("apcs"))
- return ARMBaseTargetMachine::ARM_ABI_APCS;
-
- llvm_unreachable("Unhandled/unknown ABI Name!");
- return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
-}
-
static std::string computeDataLayout(const Triple &TT, StringRef CPU,
const TargetOptions &Options,
bool isLittle) {
- auto ABI = computeTargetABI(TT, CPU, Options);
+ auto ABI = ARM::computeTargetABI(TT, CPU, Options.MCOptions.ABIName);
std::string Ret;
if (isLittle)
@@ -163,19 +144,19 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU,
Ret += "-Fi8";
// ABIs other than APCS have 64 bit integers with natural alignment.
- if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
+ if (ABI != ARM::ARM_ABI_APCS)
Ret += "-i64:64";
// We have 64 bits floats. The APCS ABI requires them to be aligned to 32
// bits, others to 64 bits. We always try to align to 64 bits.
- if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
+ if (ABI == ARM::ARM_ABI_APCS)
Ret += "-f64:32:64";
// We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
// to 64. We always ty to give them natural alignment.
- if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
+ if (ABI == ARM::ARM_ABI_APCS)
Ret += "-v64:32:64-v128:32:128";
- else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
+ else if (ABI != ARM::ARM_ABI_AAPCS16)
Ret += "-v128:64:128";
// Try to align aggregates to 32 bits (the default is 64 bits, which has no
@@ -187,9 +168,9 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU,
// The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
// aligned everywhere else.
- if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
+ if (TT.isOSNaCl() || ABI == ARM::ARM_ABI_AAPCS16)
Ret += "-S128";
- else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
+ else if (ABI == ARM::ARM_ABI_AAPCS)
Ret += "-S64";
else
Ret += "-S32";
@@ -226,7 +207,7 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
TT, CPU, FS, Options,
getEffectiveRelocModel(TT, RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
- TargetABI(computeTargetABI(TT, CPU, Options)),
+ TargetABI(ARM::computeTargetABI(TT, CPU, Options.MCOptions.ABIName)),
TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
// Default to triple-appropriate float ABI
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h
index 99fd817c81f89..4a2e9f41376f9 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.h
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.h
@@ -20,6 +20,7 @@
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/TargetParser/ARMTargetParser.h"
#include <memory>
#include <optional>
@@ -27,12 +28,7 @@ namespace llvm {
class ARMBaseTargetMachine : public CodeGenTargetMachineImpl {
public:
- enum ARMABI {
- ARM_ABI_UNKNOWN,
- ARM_ABI_APCS,
- ARM_ABI_AAPCS, // ARM EABI
- ARM_ABI_AAPCS16
- } TargetABI;
+ ARM::ARMABI TargetABI;
protected:
std::unique_ptr<TargetLoweringObjectFile> TLOF;
@@ -73,8 +69,7 @@ class ARMBaseTargetMachine : public CodeGenTargetMachineImpl {
TargetTriple.getEnvironment() == Triple::EABIHF ||
(TargetTriple.isOSBinFormatMachO() &&
TargetTriple.getSubArch() == Triple::ARMSubArch_v7em) ||
- TargetTriple.isOSWindows() ||
- TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
+ TargetTriple.isOSWindows() || TargetABI == ARM::ARM_ABI_AAPCS16;
}
bool targetSchedulesPostRAScheduling() const override { return true; };
diff --git a/llvm/lib/Target/ARM/ARMTargetObjectFile.cpp b/llvm/lib/Target/ARM/ARMTargetObjectFile.cpp
index a0a400f938482..cf84f1043cc69 100644
--- a/llvm/lib/Target/ARM/ARMTargetObjectFile.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetObjectFile.cpp
@@ -37,7 +37,7 @@ ARMElfTargetObjectFile::ARMElfTargetObjectFile() {
void ARMElfTargetObjectFile::Initialize(MCContext &Ctx,
const TargetMachine &TM) {
const ARMBaseTargetMachine &ARM_TM = static_cast<const ARMBaseTargetMachine &>(TM);
- bool isAAPCS_ABI = ARM_TM.TargetABI == ARMBaseTargetMachine::ARMABI::ARM_ABI_AAPCS;
+ bool isAAPCS_ABI = ARM_TM.TargetABI == ARM::ARMABI::ARM_ABI_AAPCS;
bool genExecuteOnly =
ARM_TM.getMCSubtargetInfo()->hasFeature(ARM::FeatureExecuteOnly);
diff --git a/llvm/lib/TargetParser/ARMTargetParser.cpp b/llvm/lib/TargetParser/ARMTargetParser.cpp
index a7a895d872668..9ff6521c5d1e8 100644
--- a/llvm/lib/TargetParser/ARMTargetParser.cpp
+++ b/llvm/lib/TargetParser/ARMTargetParser.cpp
@@ -575,6 +575,23 @@ StringRef ARM::computeDefaultTargetABI(const Triple &TT, StringRef CPU) {
}
}
+ARM::ARMABI ARM::computeTargetABI(const Triple &TT, StringRef CPU,
+ StringRef ABIName) {
+ if (ABIName.empty())
+ ABIName = ARM::computeDefaultTargetABI(TT, CPU);
+
+ if (ABIName == "aapcs16")
+ return ARM_ABI_AAPCS16;
+
+ if (ABIName.starts_with("aapcs"))
+ return ARM_ABI_AAPCS;
+
+ if (ABIName.starts_with("apcs"))
+ return ARM_ABI_APCS;
+
+ return ARM_ABI_UNKNOWN;
+}
+
StringRef ARM::getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch) {
if (MArch.empty())
MArch = Triple.getArchName();
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