[llvm] [AMDGPU][True16][CodeGen] sext i16 inreg in true16 mode (PR #144024)

[Brox Chen via llvm-commits]

broxigarchen wrote:

Update the test with dim 8 in vector shuffle. Here is the old code with the problem
```
IR:
  %tid = call i32 @llvm.amdgcn.workitem.id.x()
  %in.gep = getelementptr <{ [0 x i8] }>, ptr addrspace(1) %ptr, i64 0, i32 0, i32 %tid
  %load = load <8 x i8>, ptr addrspace(1) %in.gep
  %shuff = shufflevector <8 x i8> %load, <8 x i8> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
  %cast = sitofp <8 x i8> %shuff to <8 x half>
  store <8 x half> %cast, ptr addrspace(1) %out

; GFX11-TRUE16-NEXT:    global_load_b64 v[1:2], v0, s[2:3]
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v1.l
; GFX11-TRUE16-NEXT:    v_bfe_i32 v5, v2, 0, 8
; GFX11-TRUE16-NEXT:    v_bfe_i32 v4, v1, 0, 8
; GFX11-TRUE16-NEXT:    v_ashrrev_i32_e32 v6, 24, v2
; GFX11-TRUE16-NEXT:    v_ashrrev_i16 v0.l, 8, v1.l
; GFX11-TRUE16-NEXT:    v_bfe_i32 v7, v3, 0, 8
; GFX11-TRUE16-NEXT:    v_ashrrev_i16 v0.h, 8, v2.l
; GFX11-TRUE16-NEXT:    v_ashrrev_i32_e32 v2, 24, v1
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v5.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v4.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v7.l
; GFX11-TRUE16-NEXT:    v_cvt_f16_i16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT:    v_cvt_f16_i16_e32 v0.h, v0.h
; GFX11-TRUE16-NEXT:    v_cvt_f16_i16_e32 v2.l, v2.l
; GFX11-TRUE16-NEXT:    v_cvt_f16_i16_e32 v4.h, v6.l
; GFX11-TRUE16-NEXT:    v_cvt_f16_i16_e32 v1.l, v1.l
; GFX11-TRUE16-NEXT:    v_cvt_f16_i16_e32 v2.h, v3.l
; GFX11-TRUE16-NEXT:    v_cvt_f16_i16_e32 v3.l, v4.l
; GFX11-TRUE16-NEXT:    v_cvt_f16_i16_e32 v4.l, v5.l
; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, 0
; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v0.h, v1.l
; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v2, v2.l, v2.h
; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v3, v0.l, v3.l
; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v4.h, v4.l
; GFX11-TRUE16-NEXT:    global_store_b128 v5, v[0:3], s[0:1]
```
At the output, v0.h is the indexed 1 output i8 and it's expected to be the indexed 6 i8 from input.

However, the chain flow:
```
v_bfe_i32 v5, v2, 0, 8
v_cvt_f16_i16_e32 v4.l, v5.l
v_pack_b32_f16 v0, v4.h, v4.l
```
It's equal to v0.h = v2 & 0xff which is the indexed 5 i8 from input

https://github.com/llvm/llvm-project/pull/144024