[llvm] [RISCV] Switch to sign-extended loads if possible in RISCVOptWInstrs (PR #144703)

[via llvm-commits]

github-actions[bot] wrote:

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You can test this locally with the following command:
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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index a141bae55..3f01b276d 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -72,7 +72,7 @@ public:
   bool appendWSuffixes(MachineFunction &MF, const RISCVInstrInfo &TII,
                        const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
   bool convertZExtLoads(MachineFunction &MF, const RISCVInstrInfo &TII,
-                       const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
+                        const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
@@ -791,9 +791,9 @@ bool RISCVOptWInstrs::appendWSuffixes(MachineFunction &MF,
 }
 
 bool RISCVOptWInstrs::convertZExtLoads(MachineFunction &MF,
-                                      const RISCVInstrInfo &TII,
-                                      const RISCVSubtarget &ST,
-                                      MachineRegisterInfo &MRI) {
+                                       const RISCVInstrInfo &TII,
+                                       const RISCVSubtarget &ST,
+                                       MachineRegisterInfo &MRI) {
   bool MadeChange = false;
   for (MachineBasicBlock &MBB : MF) {
     for (MachineInstr &MI : MBB) {

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https://github.com/llvm/llvm-project/pull/144703