[llvm] [RISCV] Add support for handling one tied operand in the source instruction for compress patterns (PR #143660)

[via llvm-commits]

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@@ -123,7 +124,7 @@ class CompressInstEmitter {
   const RecordKeeper &Records;
   const CodeGenTarget Target;
   std::vector<CompressPat> CompressPatterns;
-
+  unsigned SourceLastTiedOp; // postion of the last tied operand in Source Inst
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hchandel wrote:

Thanks. Done

https://github.com/llvm/llvm-project/pull/143660