[llvm] [feature][riscv] handle target address calculation in llvm-objdump disassembly for riscv (PR #144620)
Arjun Patel via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 17 21:18:41 PDT 2025
https://github.com/arjunUpatel updated https://github.com/llvm/llvm-project/pull/144620
>From 52ebb65f8c0879a7e75295b3c3aae9acaeb5d57e Mon Sep 17 00:00:00 2001
From: Arjun Patel <arjunpatel151002 at gmail.com>
Date: Tue, 10 Jun 2025 19:33:37 -0400
Subject: [PATCH 1/5] Remove changes affecting non-RISCV targets
---
llvm/include/llvm/MC/MCInstrAnalysis.h | 5 +
llvm/lib/MC/MCInstrAnalysis.cpp | 6 +
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 113 ++++++++++++++++--
.../tools/llvm-objdump/RISCV/Inputs/riscv-ar | Bin 0 -> 1062552 bytes
.../RISCV/Inputs/riscv-ar-coverage | Bin 0 -> 1058216 bytes
.../tools/llvm-objdump/RISCV/lit.local.cfg | 2 +
.../llvm-objdump/RISCV/riscv-ar-coverage.s | 111 +++++++++++++++++
llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s | 57 +++++++++
llvm/tools/llvm-objdump/llvm-objdump.cpp | 11 +-
9 files changed, 290 insertions(+), 15 deletions(-)
create mode 100644 llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar
create mode 100644 llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar-coverage
create mode 100644 llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg
create mode 100644 llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s
create mode 100644 llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s
diff --git a/llvm/include/llvm/MC/MCInstrAnalysis.h b/llvm/include/llvm/MC/MCInstrAnalysis.h
index 63a4e02a92360..1f05e8546c3d1 100644
--- a/llvm/include/llvm/MC/MCInstrAnalysis.h
+++ b/llvm/include/llvm/MC/MCInstrAnalysis.h
@@ -182,6 +182,11 @@ class LLVM_ABI MCInstrAnalysis {
evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
uint64_t &Target) const;
+ /// Given an instruction that accesses a memory address, try to compute
+ /// the target address. Return true on success, and the address in \p Target.
+ virtual bool evaluateInstruction(const MCInst &Inst, uint64_t Addr,
+ uint64_t Size, uint64_t &Target) const;
+
/// Given an instruction tries to get the address of a memory operand. Returns
/// the address on success.
virtual std::optional<uint64_t>
diff --git a/llvm/lib/MC/MCInstrAnalysis.cpp b/llvm/lib/MC/MCInstrAnalysis.cpp
index cea905d092e0b..1ae0c91a2590c 100644
--- a/llvm/lib/MC/MCInstrAnalysis.cpp
+++ b/llvm/lib/MC/MCInstrAnalysis.cpp
@@ -30,6 +30,12 @@ bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
return false;
}
+bool MCInstrAnalysis::evaluateInstruction(const MCInst &Inst, uint64_t Addr,
+ uint64_t Size,
+ uint64_t &Target) const {
+ return false;
+}
+
std::optional<uint64_t> MCInstrAnalysis::evaluateMemoryOperandAddress(
const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
uint64_t Size) const {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index f3b93f032588c..e52f5e50832c7 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -29,7 +29,9 @@
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/MathExtras.h"
#include <bitset>
+#include <cstdint>
#define GET_INSTRINFO_MC_DESC
#define ENABLE_INSTR_PREDICATE_VERIFIER
@@ -129,6 +131,7 @@ namespace {
class RISCVMCInstrAnalysis : public MCInstrAnalysis {
int64_t GPRState[31] = {};
std::bitset<31> GPRValidMask;
+ unsigned int ArchRegWidth;
static bool isGPR(MCRegister Reg) {
return Reg >= RISCV::X0 && Reg <= RISCV::X31;
@@ -165,8 +168,8 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
public:
- explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
- : MCInstrAnalysis(Info) {}
+ explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info, unsigned int ArchRegWidth)
+ : MCInstrAnalysis(Info), ArchRegWidth(ArchRegWidth) {}
void resetState() override { GPRValidMask.reset(); }
@@ -182,6 +185,17 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
switch (Inst.getOpcode()) {
+ case RISCV::C_LUI:
+ case RISCV::LUI: {
+ setGPRState(Inst.getOperand(0).getReg(),
+ SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
+ break;
+ }
+ case RISCV::AUIPC: {
+ setGPRState(Inst.getOperand(0).getReg(),
+ Addr + SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
+ break;
+ }
default: {
// Clear the state of all defined registers for instructions that we don't
// explicitly support.
@@ -193,10 +207,6 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
break;
}
- case RISCV::AUIPC:
- setGPRState(Inst.getOperand(0).getReg(),
- Addr + SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
- break;
}
}
@@ -234,6 +244,83 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
return false;
}
+ bool evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
+ uint64_t &Target) const override {
+ switch(Inst.getOpcode()) {
+ default:
+ return false;
+ case RISCV::C_ADDI:
+ case RISCV::ADDI: {
+ MCRegister Reg = Inst.getOperand(1).getReg();
+ auto TargetRegState = getGPRState(Reg);
+ if (TargetRegState && Reg != RISCV::X0) {
+ Target = *TargetRegState + Inst.getOperand(2).getImm();
+ Target &= maskTrailingOnes<uint64_t>(ArchRegWidth);
+ return true;
+ }
+ break;
+ }
+ case RISCV::C_ADDIW:
+ case RISCV::ADDIW: {
+ MCRegister Reg = Inst.getOperand(1).getReg();
+ auto TargetRegState = getGPRState(Reg);
+ if (TargetRegState && Reg != RISCV::X0) {
+ Target = *TargetRegState + Inst.getOperand(2).getImm();
+ Target = SignExtend64<32>(Target);
+ return true;
+ }
+ break;
+ }
+ case RISCV::LB:
+ case RISCV::LH:
+ case RISCV::LD:
+ case RISCV::LW:
+ case RISCV::LBU:
+ case RISCV::LHU:
+ case RISCV::LWU:
+ case RISCV::SB:
+ case RISCV::SH:
+ case RISCV::SW:
+ case RISCV::SD:
+ case RISCV::FLH:
+ case RISCV::FLW:
+ case RISCV::FLD:
+ case RISCV::FSH:
+ case RISCV::FSW:
+ case RISCV::FSD:
+ case RISCV::C_LD:
+ case RISCV::C_SD:
+ case RISCV::C_FLD:
+ case RISCV::C_FSD:
+ case RISCV::C_SW:
+ case RISCV::C_LW:
+ case RISCV::C_FSW:
+ case RISCV::C_FLW:
+ case RISCV::C_LBU:
+ case RISCV::C_LH:
+ case RISCV::C_LHU:
+ case RISCV::C_SB:
+ case RISCV::C_SH:
+ case RISCV::C_LWSP:
+ case RISCV::C_SWSP:
+ case RISCV::C_LDSP:
+ case RISCV::C_SDSP:
+ case RISCV::C_FLWSP:
+ case RISCV::C_FSWSP:
+ case RISCV::C_FLDSP:
+ case RISCV::C_FSDSP: {
+ MCRegister Reg = Inst.getOperand(1).getReg();
+ auto TargetRegState = getGPRState(Reg);
+ if (TargetRegState && Reg != RISCV::X0) {
+ Target = *TargetRegState + Inst.getOperand(2).getImm();
+ return true;
+ }
+ break;
+ }
+ }
+ return false;
+ }
+
bool isTerminator(const MCInst &Inst) const override {
if (MCInstrAnalysis::isTerminator(Inst))
return true;
@@ -327,8 +414,12 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
} // end anonymous namespace
-static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) {
- return new RISCVMCInstrAnalysis(Info);
+static MCInstrAnalysis *createRISCV32InstrAnalysis(const MCInstrInfo *Info) {
+ return new RISCVMCInstrAnalysis(Info, 32);
+}
+
+static MCInstrAnalysis *createRISCV64InstrAnalysis(const MCInstrInfo *Info) {
+ return new RISCVMCInstrAnalysis(Info, 64);
}
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
@@ -344,12 +435,14 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
TargetRegistry::RegisterELFStreamer(*T, createRISCVELFStreamer);
TargetRegistry::RegisterObjectTargetStreamer(
*T, createRISCVObjectTargetStreamer);
- TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis);
-
// Register the asm target streamer.
TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
// Register the null target streamer.
TargetRegistry::RegisterNullTargetStreamer(*T,
createRISCVNullTargetStreamer);
}
+ TargetRegistry::RegisterMCInstrAnalysis(getTheRISCV32Target(),
+ createRISCV32InstrAnalysis);
+ TargetRegistry::RegisterMCInstrAnalysis(getTheRISCV64Target(),
+ createRISCV64InstrAnalysis);
}
diff --git a/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar b/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar
new file mode 100644
index 0000000000000000000000000000000000000000..bc335bc24f88d8577308802b27dbded31834a89f
GIT binary patch
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diff --git a/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar-coverage b/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar-coverage
new file mode 100644
index 0000000000000000000000000000000000000000..08ba4f884605001094c28ce355201e6842b8d08f
GIT binary patch
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HcmV?d00001
diff --git a/llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg b/llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg
new file mode 100644
index 0000000000000..17351748513d9
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg
@@ -0,0 +1,2 @@
+if not "RISCV" in config.root.targets:
+ config.unsupported = True
diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s
new file mode 100644
index 0000000000000..ec32e53fce0ca
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s
@@ -0,0 +1,111 @@
+# RUN: llvm-objdump -d %p/Inputs/riscv-ar-coverage | FileCheck %s
+
+# CHECK: 0000000000001000 <_start>:
+# CHECK-NEXT: 1000: 00001517 auipc a0, 0x1
+# CHECK-NEXT: 1004: 00450513 addi a0, a0, 0x4 <target>
+# CHECK-NEXT: 1008: 00001517 auipc a0, 0x1
+# CHECK-NEXT: 100c: 1571 addi a0, a0, -0x4 <target>
+# CHECK-NEXT: 100e: 6509 lui a0, 0x2
+# CHECK-NEXT: 1010: 0045059b addiw a1, a0, 0x4 <target>
+# CHECK-NEXT: 1014: 6509 lui a0, 0x2
+# CHECK-NEXT: 1016: 2511 addiw a0, a0, 0x4 <target>
+# CHECK-NEXT: 1018: 00102537 lui a0, 0x102
+# CHECK-NEXT: 101c: c50c sw a1, 0x8(a0) <far_target>
+# CHECK-NEXT: 101e: 00102537 lui a0, 0x102
+# CHECK-NEXT: 1022: 4508 lw a0, 0x8(a0) <far_target>
+# CHECK-NEXT: 1024: 6509 lui a0, 0x2
+# CHECK-NEXT: 1026: 6585 lui a1, 0x1
+# CHECK-NEXT: 1028: 0306 slli t1, t1, 0x1
+# CHECK-NEXT: 102a: 0511 addi a0, a0, 0x4 <target>
+# CHECK-NEXT: 102c: 0505 addi a0, a0, 0x1
+# CHECK-NEXT: 102e: 00200037 lui zero, 0x200
+# CHECK-NEXT: 1032: 00a02423 sw a0, 0x8(zero)
+# CHECK-NEXT: 1036: 00101097 auipc ra, 0x101
+# CHECK-NEXT: 103a: fd6080e7 jalr -0x2a(ra) <func>
+# CHECK-NEXT: 103e: 00102437 lui s0, 0x102
+# CHECK-NEXT: 1042: 8800 sb s0, 0x0(s0) <target+0xffffc>
+# CHECK-NEXT: 1044: 00102137 lui sp, 0x102
+# CHECK-NEXT: 1048: 4522 lw a0, 0x8(sp) <far_target>
+
+.global _start
+.text
+
+# The core of the feature being added was address resolution for instruction
+# sequences where a register is populated by immediate values via two
+# separate instructions. First by an instruction that provides the upper bits
+# (auipc, lui ...) followed by another instruction for the lower bits (addi,
+# jalr, ld ...).
+
+
+_start:
+ # Test block 1-3 each focus on a certain starting instruction in a sequences,
+ # the ones that provide the upper bits. The other sequence is another
+ # instruction the provides the lower bits. The second instruction is
+ # arbitrarily chosen to increase code coverage
+
+ # test block #1
+ lla a0, target # addi
+ auipc a0, 0x1
+ c.addi a0, -0x4 # c.addi
+
+ # test block #2
+ c.lui a0, 0x2
+ addiw a1, a0, 0x4 # addiw
+ c.lui a0, 0x2
+ c.addiw a0, 0x4 # c.addiw
+
+ # test block #3
+ lui a0, 0x102
+ sw a1, 0x8(a0) # sw
+ lui a0, 0x102
+ c.lw a0, 0x8(a0) # lw
+
+ # Test block 4 tests instruction interleaving, essentially the code's
+ # ability to keep track of a valid sequence even if multiple other unrelated
+ # instructions separate the two
+
+ # test #4
+ lui a0, 0x2
+ lui a1, 0x1 # unrelated instruction
+ slli t1, t1, 0x1 # unrelated instruction
+ addi a0, a0, 0x4
+ addi a0, a0, 0x1
+
+ # Test 5 ensures that an instruction writing into the zero register does
+ # not trigger resolution because that register's value cannot change and
+ # the sequence is equivalent to never running the first instruction
+
+ # test #5
+ lui x0, 0x200
+ sw a0, 0x8(x0)
+
+ # Test 6 ensures that the newly added functionality is compatible with
+ # code that already worked for branch instructions
+
+ # test #6
+ call func
+
+ # test #7 zcb extension
+ lui x8, 0x102
+ # the immediate value for Zcb extension is heavily bounded, so we will relax
+ # the requirement of hitting one of the labels and focus on correctness of the
+ # resolution. This can be verified by looking at the source: The upper bits of
+ # lui make the far jump related to .skip 0x100000 and then 8 more bytes must be
+ # traversed before we hit far_target--.skip 0x4 and .word 1 in target. Adding 8
+ # to address resolved for the instruction below yields exactly the desired label.
+ c.sb x8, 0(x8)
+
+ # test #8 stack based load/stores
+ lui sp, 0x102
+ c.lwsp a0, 0x8(sp)
+
+# these are the labels that the instructions above are expecteed to resolve to
+.section .data
+.skip 0x4
+target:
+ .word 1
+.skip 0x100000
+far_target:
+ .word 2
+func:
+ ret
diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s
new file mode 100644
index 0000000000000..49225519a62df
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s
@@ -0,0 +1,57 @@
+# RUN: llvm-objdump -d %p/Inputs/riscv-ar | FileCheck %s
+
+# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: ld a0, {{-?0x[0-9a-fA-F]+}}(a0) <ldata+0xfa4>
+# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}} <gdata>
+# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}} <gdata>
+# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: lw a0, {{-?0x[0-9a-fA-F]+}}(a0) <gdata>
+# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}} <ldata>
+# CHECK: auipc ra, {{-?0x[0-9a-fA-F]+}}
+# CHECK: jalr {{-?0x[0-9a-fA-F]+}}(ra) <func>
+# CHECK: auipc t1, {{-?0x[0-9a-fA-F]+}}
+# CHECK: jr {{-?0x[0-9a-fA-F]+}}(t1) <func>
+# CHECK: lui a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addiw a0, a0, {{-?0x[0-9a-fA-F]+}} <gdata+0x12242678>
+# CHECK: lui a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addiw a0, a0, {{-?0x[0-9a-fA-F]+}} <gdata+0x1438ad>
+# CHECK: slli a0, a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: slli a0, a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: slli a0, a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: lui a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: lui a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addiw a0, a0, {{-?0x[0-9a-fA-F]+}} <_start+0xfefff>
+
+.global _start
+.text
+_start:
+ la a0, gdata
+ lla a0, gdata
+ lla a0, gdata
+ lw a0, gdata
+ lla a0, ldata
+
+ call func
+ tail func
+
+ li a0, 0x12345678
+ li a0, 0x1234567890abcdef
+ li a0, 0x10000
+ li a0, 0xfffff
+
+ .skip 0x100000
+func:
+ ret
+
+ldata:
+ .int 0
+
+.data
+gdata:
+ .int 0
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index 5ecb33375943f..b5d316e1e3857 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -1520,8 +1520,8 @@ collectLocalBranchTargets(ArrayRef<uint8_t> Bytes, MCInstrAnalysis *MIA,
if (MIA) {
if (Disassembled) {
uint64_t Target;
- bool TargetKnown = MIA->evaluateBranch(Inst, Index, Size, Target);
- if (TargetKnown && (Target >= Start && Target < End) &&
+ bool BranchTargetKnown = MIA->evaluateBranch(Inst, Index, Size, Target);
+ if (BranchTargetKnown && (Target >= Start && Target < End) &&
!Targets.count(Target)) {
// On PowerPC and AIX, a function call is encoded as a branch to 0.
// On other PowerPC platforms (ELF), a function call is encoded as
@@ -2356,8 +2356,9 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
llvm::raw_ostream *TargetOS = &FOS;
uint64_t Target;
bool PrintTarget = DT->InstrAnalysis->evaluateBranch(
- Inst, SectionAddr + Index, Size, Target);
-
+ Inst, SectionAddr + Index, Size, Target) ||
+ DT->InstrAnalysis->evaluateInstruction(
+ Inst, SectionAddr + Index, Size, Target);
if (!PrintTarget) {
if (std::optional<uint64_t> MaybeTarget =
DT->InstrAnalysis->evaluateMemoryOperandAddress(
@@ -2430,7 +2431,7 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
break;
}
- // Branch targets are printed just after the instructions.
+ // Branch and instruction targets are printed just after the instructions.
// Print the labels corresponding to the target if there's any.
bool BBAddrMapLabelAvailable = BBAddrMapLabels.count(Target);
bool LabelAvailable = AllLabels.count(Target);
>From 49f276ea9b2e93e36b298a4130bf7d9a9f4f8f76 Mon Sep 17 00:00:00 2001
From: Arjun Patel <arjunpatel151002 at gmail.com>
Date: Thu, 12 Jun 2025 16:15:11 -0400
Subject: [PATCH 2/5] Update test output to match previous functionality
As a result of the force push, the context of the old commit history was erased. In the previous iteration changes were made to llvm-objdump which affected non-riscv targets. It was decided to move these changes to another PR. This commit continues the reversion of that iteration
---
llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s
index 49225519a62df..72e5f586b721e 100644
--- a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s
+++ b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s
@@ -1,7 +1,7 @@
# RUN: llvm-objdump -d %p/Inputs/riscv-ar | FileCheck %s
# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
-# CHECK: ld a0, {{-?0x[0-9a-fA-F]+}}(a0) <ldata+0xfa4>
+# CHECK: ld a0, {{-?0x[0-9a-fA-F]+}}(a0)
# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}} <gdata>
# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
>From 5e1cf1263e09f453146b75c333e3ffa2dbcc5710 Mon Sep 17 00:00:00 2001
From: Arjun Patel <arjunpatel151002 at gmail.com>
Date: Tue, 17 Jun 2025 19:36:47 -0400
Subject: [PATCH 3/5] Add support for zclsd and zilsd extensions + tests
---
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 8 ++++-
.../RISCV/Inputs/riscv32-ar-coverage | Bin 0 -> 9140 bytes
...{riscv-ar-coverage => riscv64-ar-coverage} | Bin 1058216 -> 1058272 bytes
.../llvm-objdump/RISCV/riscv32-ar-coverage.s | 30 ++++++++++++++++
...cv-ar-coverage.s => riscv64-ar-coverage.s} | 33 ++++++++----------
5 files changed, 51 insertions(+), 20 deletions(-)
create mode 100755 llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv32-ar-coverage
rename llvm/test/tools/llvm-objdump/RISCV/Inputs/{riscv-ar-coverage => riscv64-ar-coverage} (99%)
mode change 100644 => 100755
create mode 100644 llvm/test/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
rename llvm/test/tools/llvm-objdump/RISCV/{riscv-ar-coverage.s => riscv64-ar-coverage.s} (76%)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index e52f5e50832c7..1ffdca4125fab 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -308,7 +308,13 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
case RISCV::C_FLWSP:
case RISCV::C_FSWSP:
case RISCV::C_FLDSP:
- case RISCV::C_FSDSP: {
+ case RISCV::C_FSDSP:
+ case RISCV::C_LD_RV32:
+ case RISCV::C_SD_RV32:
+ case RISCV::C_SDSP_RV32:
+ case RISCV::LD_RV32:
+ case RISCV::C_LDSP_RV32:
+ case RISCV::SD_RV32: {
MCRegister Reg = Inst.getOperand(1).getReg();
auto TargetRegState = getGPRState(Reg);
if (TargetRegState && Reg != RISCV::X0) {
diff --git a/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv32-ar-coverage b/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv32-ar-coverage
new file mode 100755
index 0000000000000000000000000000000000000000..8ac5ea52258a1d08b5b96843c64cc9fc52c4db54
GIT binary patch
literal 9140
zcmeHNO=}ZT6uoJUt+q=2sv;sOR&e9c#EL}(TWl?2EC`Bpl}=}-&0uB{W+pW)g05V-
z@=v(&C)A}s#UCJ|8^L(an|UF&8 at qFHFFkY5{d#$GvMRZ6R_YH+rIJ`1mG5GrDUo?3
zKh21g;pe3y<8nhz$%Gs?ab9PS8NkpnP+}CAM{F^Um|zX*{Cs$8pOGY37kn;z=nsPT
zU~UBNHJU6I5fk?FpMK4Jgoljxrm^oH<}EHEChR=!-;oLuh4tVG)_J#<@1$*~YGS?@
z-*<KGxqLX&|G2tPdW`Td<BY}Sp~_Wo&j0H7+o+H8e$PNA;Q9J|-+ja<;W_`~cfakE
zsHp;~fGVI0r~;~hDxeCe0;+&2pbDr0M^xY<{>fY~^EnmrdF}R>Bc7n`s(>n>3aA3A
zfGVI0r~;~hDxeCe0;+&2 at V_gt^a?jj!qnT5QUqE~c5c<eTBq8GYMr@;OSV<()EYh?
zd!d&m%<qL;LF@%+ByXjDl_ZL~Ekj&4YUiYtq at H1(o4dSM>S6pcNbXkZ_2o)+!Kpe6
zhm|rvb at PXCV`Jv`_VYvW81mCY@#zEc*?h2ge(PTW<IaGwk+NJMDdwjHr#WGq1xZJo
zxSa*gcHDI~yJ5?}8T#V*yK%Z3iODwIv}rPK6nc3nOT@{7UM7wa({Zyb2{*f0kc#8A
zqbP_`!U37P3Exb!Bxkvo*`Cb$lDWxtkVyg{YNUuWX)Ld=Ej at YkAiws%Jo$<Q_augQ
zFzl?A-~<xXkbT3u5Vnu|4m9e<odouAKY^fZ+*jaP>|;C&{KPH;`?#k-aIb><5j1<A
z1I}6Y@%tbaiyYiwui_3kXW6%p9s+*@v;00X<YvEv7XhXRUHLr26#(aT2Bk{A*I{FO
z-U}qi=ZZqFB66<abgU5 at 0Pkk)eMRIgf=Ph7T3wppRs&F(oDtb0DU4^)5 at 5LR9r~`D
JO8&5Ye*m?Pl-~dV
literal 0
HcmV?d00001
diff --git a/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar-coverage b/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv64-ar-coverage
old mode 100644
new mode 100755
similarity index 99%
rename from llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar-coverage
rename to llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv64-ar-coverage
index 08ba4f884605001094c28ce355201e6842b8d08f..ceaf049b9a4fef2f01a311a6b5351dd31b5c931a
GIT binary patch
delta 487
zcmZ9Jze_?<6vyv<srfYXh=@u<$H$YDf^2JuRIoYx3-tNS2(-i>p)UOzYzYj98x2w|
zIR*|c4LJ+_3q^C#+St+e3hBV-e$V|LF86!6{c+-boajV&_B#3|r<hTxfrq=f+%&h%
zZd6*aUp+oFcb{9!-FqGwl%-df&6Q`D%Fe)pFK*F6u!)`mjsfE5%=QAYjmQa!m?JEN
zm9P=>gq at HH2jL_Z2p6$9M09_Dc_m75ewu8MR1T{8G2 at 3~31MrkRH_#@%CSsK(@IB1
zQ>;|=X{T$3<P6D+EJCdN#I2K{fuLpjGCQ;2wE0_{VuavVz#OxGWACpY6CViMJS;*X
z at CVl?wq#|UNz|E&h;#^URaVm~`+GH3s2}P~&9j!CV+E~}F>SR$rtm6|?v^F{u&lrh
z=P4npaKfA748bRQDk!`yMk>U8cW9>L#!W5~hwz1AmG?z53~@PP=HE0A)2I9Z0ugHV
delta 387
zcmaEG+F`|MhY1>t8WT0|b9ymAfY)Y0Mt(-lFeo={vL=%{ha1D6-!InbC{13-D6zSK
z=^QVQxrzV-Lx;Jd0E3e2W<iBr{7nXJ28?Y6Ol=0tZ3ZlD2CQucY;6YYZ3Y}|2ApjM
zTx|y2Z3aAT2E1(seA^88IX-L_F!;kiJwQc(g}<r6F%)QDQD$*+83UvDbZG?v8_wiJ
z!vcf&s^p~U%?bhrlML9V?^6&EVq}|sQ9(dlk{9eg4h9|tpgWL&&~!#c0rBYuiUJ0V
z>eCZ}Y)NB~G!rYs1STYPK&H<0iHZWVH1rG at N)n6GQ%e}qO7oH#R8sT|8PXDq;-P{n
z6?#S>LF4KEN&<nCH!!knU!WwgfRWK_x}%CfJ!9DPgDL{%j49K9stDMNRzRKe0csV<
enVi#oRRy#eGp1Ln3fObL00tQd*i8PYFAo6TL0BCC
diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s b/llvm/test/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
new file mode 100644
index 0000000000000..2e1a109f9ec86
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/RISCV/riscv32-ar-coverage.s
@@ -0,0 +1,30 @@
+# RUN: llvm-objdump -d %p/Inputs/riscv32-ar-coverage | FileCheck %s
+
+# CHECK: 00001000 <_start>:
+# CHECK-NEXT: 1000: 00000517 auipc a0, 0x0
+# CHECK-NEXT: 1004: 0559 addi a0, a0, 0x16 <target>
+# CHECK-NEXT: 1006: 00000517 auipc a0, 0x0
+# CHECK-NEXT: 100a: 6910 ld a2, 0x10(a0) <target>
+# CHECK-NEXT: 100c: 00000517 auipc a0, 0x0
+# CHECK-NEXT: 1010: 00c53523 sd a2, 0xa(a0) <target>
+# CHECK-NEXT: 1014: 0000 unimp
+
+# the structure of this test file is similar to that of riscv64-ar-coverage
+# with the major difference being that these tests are focused on instructions
+# for 32 bit architecture
+
+.global _start
+.text
+_start:
+ auipc a0, 0x0
+ addi a0, a0, 0x16 # addi -- behavior changes with differentr architectures
+
+ auipc a0, 0x0
+ c.ld a2, 0x10(a0) # zclsd instruction
+
+ auipc a0, 0x0
+ sd a2, 0xa(a0) # zilsd instruction
+
+.skip 0x2
+target:
+ ret:
diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s b/llvm/test/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
similarity index 76%
rename from llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s
rename to llvm/test/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
index ec32e53fce0ca..003defd351dfd 100644
--- a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s
+++ b/llvm/test/tools/llvm-objdump/RISCV/riscv64-ar-coverage.s
@@ -1,4 +1,4 @@
-# RUN: llvm-objdump -d %p/Inputs/riscv-ar-coverage | FileCheck %s
+# RUN: llvm-objdump -d %p/Inputs/riscv64-ar-coverage | FileCheck %s
# CHECK: 0000000000001000 <_start>:
# CHECK-NEXT: 1000: 00001517 auipc a0, 0x1
@@ -22,23 +22,22 @@
# CHECK-NEXT: 1032: 00a02423 sw a0, 0x8(zero)
# CHECK-NEXT: 1036: 00101097 auipc ra, 0x101
# CHECK-NEXT: 103a: fd6080e7 jalr -0x2a(ra) <func>
-# CHECK-NEXT: 103e: 00102437 lui s0, 0x102
-# CHECK-NEXT: 1042: 8800 sb s0, 0x0(s0) <target+0xffffc>
-# CHECK-NEXT: 1044: 00102137 lui sp, 0x102
-# CHECK-NEXT: 1048: 4522 lw a0, 0x8(sp) <far_target>
+# CHECK-NEXT: 103e: 640d lui s0, 0x3
+# CHECK-NEXT: 1040: 8800 sb s0, 0x0(s0) <zcb>
+# CHECK-NEXT: 1042: 4522 lw a0, 0x8(sp)
+
.global _start
.text
-# The core of the feature being added was address resolution for instruction
-# sequences where a register is populated by immediate values via two
+# The core of the feature being added was address resolution for instruction
+# sequences where an register is populated by immediate values via two
# separate instructions. First by an instruction that provides the upper bits
# (auipc, lui ...) followed by another instruction for the lower bits (addi,
# jalr, ld ...).
-
_start:
- # Test block 1-3 each focus on a certain starting instruction in a sequences,
+ # Test block 1-3 each focus on a certain starting instruction in a sequences,
# the ones that provide the upper bits. The other sequence is another
# instruction the provides the lower bits. The second instruction is
# arbitrarily chosen to increase code coverage
@@ -69,7 +68,7 @@ _start:
lui a1, 0x1 # unrelated instruction
slli t1, t1, 0x1 # unrelated instruction
addi a0, a0, 0x4
- addi a0, a0, 0x1
+ addi a0, a0, 0x1 # verify register tracking terminates
# Test 5 ensures that an instruction writing into the zero register does
# not trigger resolution because that register's value cannot change and
@@ -86,17 +85,10 @@ _start:
call func
# test #7 zcb extension
- lui x8, 0x102
- # the immediate value for Zcb extension is heavily bounded, so we will relax
- # the requirement of hitting one of the labels and focus on correctness of the
- # resolution. This can be verified by looking at the source: The upper bits of
- # lui make the far jump related to .skip 0x100000 and then 8 more bytes must be
- # traversed before we hit far_target--.skip 0x4 and .word 1 in target. Adding 8
- # to address resolved for the instruction below yields exactly the desired label.
+ lui x8, 0x3
c.sb x8, 0(x8)
# test #8 stack based load/stores
- lui sp, 0x102
c.lwsp a0, 0x8(sp)
# these are the labels that the instructions above are expecteed to resolve to
@@ -104,7 +96,10 @@ _start:
.skip 0x4
target:
.word 1
-.skip 0x100000
+.skip 0xff8
+zcb:
+ .word 1
+.skip 0xff004
far_target:
.word 2
func:
>From 11c50dccff5b68cf28c97eed83df8934dd425c68 Mon Sep 17 00:00:00 2001
From: Arjun Patel <arjunpatel151002 at gmail.com>
Date: Wed, 18 Jun 2025 00:14:23 -0400
Subject: [PATCH 4/5] Pass subtargetinfo as function argument
Follows up on discussion from linked pull request that has been closed. Essentially, not having a target specific factory method
---
llvm/include/llvm/MC/MCInstrAnalysis.h | 3 ++-
llvm/lib/MC/MCInstrAnalysis.cpp | 3 ++-
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 22 +++++++------------
llvm/tools/llvm-objdump/llvm-objdump.cpp | 2 +-
4 files changed, 13 insertions(+), 17 deletions(-)
diff --git a/llvm/include/llvm/MC/MCInstrAnalysis.h b/llvm/include/llvm/MC/MCInstrAnalysis.h
index 1f05e8546c3d1..614f220b283be 100644
--- a/llvm/include/llvm/MC/MCInstrAnalysis.h
+++ b/llvm/include/llvm/MC/MCInstrAnalysis.h
@@ -19,6 +19,7 @@
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/Compiler.h"
#include <cstdint>
#include <vector>
@@ -185,7 +186,7 @@ class LLVM_ABI MCInstrAnalysis {
/// Given an instruction that accesses a memory address, try to compute
/// the target address. Return true on success, and the address in \p Target.
virtual bool evaluateInstruction(const MCInst &Inst, uint64_t Addr,
- uint64_t Size, uint64_t &Target) const;
+ uint64_t Size, uint64_t &Target, const MCSubtargetInfo &STI) const;
/// Given an instruction tries to get the address of a memory operand. Returns
/// the address on success.
diff --git a/llvm/lib/MC/MCInstrAnalysis.cpp b/llvm/lib/MC/MCInstrAnalysis.cpp
index 1ae0c91a2590c..2dc18682eb0e3 100644
--- a/llvm/lib/MC/MCInstrAnalysis.cpp
+++ b/llvm/lib/MC/MCInstrAnalysis.cpp
@@ -32,7 +32,8 @@ bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
bool MCInstrAnalysis::evaluateInstruction(const MCInst &Inst, uint64_t Addr,
uint64_t Size,
- uint64_t &Target) const {
+ uint64_t &Target,
+ const MCSubtargetInfo &STI) const {
return false;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 1ffdca4125fab..8912ae5177a94 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -131,7 +131,6 @@ namespace {
class RISCVMCInstrAnalysis : public MCInstrAnalysis {
int64_t GPRState[31] = {};
std::bitset<31> GPRValidMask;
- unsigned int ArchRegWidth;
static bool isGPR(MCRegister Reg) {
return Reg >= RISCV::X0 && Reg <= RISCV::X31;
@@ -168,8 +167,8 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
public:
- explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info, unsigned int ArchRegWidth)
- : MCInstrAnalysis(Info), ArchRegWidth(ArchRegWidth) {}
+ explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
+ : MCInstrAnalysis(Info) {}
void resetState() override { GPRValidMask.reset(); }
@@ -245,7 +244,8 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
bool evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const override {
+ uint64_t &Target, const MCSubtargetInfo &STI) const override {
+ unsigned int ArchRegWidth = STI.getTargetTriple().getArchPointerBitWidth();
switch(Inst.getOpcode()) {
default:
return false;
@@ -420,12 +420,8 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
} // end anonymous namespace
-static MCInstrAnalysis *createRISCV32InstrAnalysis(const MCInstrInfo *Info) {
- return new RISCVMCInstrAnalysis(Info, 32);
-}
-
-static MCInstrAnalysis *createRISCV64InstrAnalysis(const MCInstrInfo *Info) {
- return new RISCVMCInstrAnalysis(Info, 64);
+static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) {
+ return new RISCVMCInstrAnalysis(Info);
}
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
@@ -446,9 +442,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
// Register the null target streamer.
TargetRegistry::RegisterNullTargetStreamer(*T,
createRISCVNullTargetStreamer);
+ TargetRegistry::RegisterMCInstrAnalysis(*T,
+ createRISCVInstrAnalysis);
}
- TargetRegistry::RegisterMCInstrAnalysis(getTheRISCV32Target(),
- createRISCV32InstrAnalysis);
- TargetRegistry::RegisterMCInstrAnalysis(getTheRISCV64Target(),
- createRISCV64InstrAnalysis);
}
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index b5d316e1e3857..3612ce9e30c6a 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -2358,7 +2358,7 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
bool PrintTarget = DT->InstrAnalysis->evaluateBranch(
Inst, SectionAddr + Index, Size, Target) ||
DT->InstrAnalysis->evaluateInstruction(
- Inst, SectionAddr + Index, Size, Target);
+ Inst, SectionAddr + Index, Size, Target, *DT->SubtargetInfo);
if (!PrintTarget) {
if (std::optional<uint64_t> MaybeTarget =
DT->InstrAnalysis->evaluateMemoryOperandAddress(
>From 22415835e2be5dc5eeca08bfbf440db1548d5708 Mon Sep 17 00:00:00 2001
From: Arjun Patel <arjunpatel151002 at gmail.com>
Date: Wed, 18 Jun 2025 00:16:37 -0400
Subject: [PATCH 5/5] Run clang format
---
llvm/include/llvm/MC/MCInstrAnalysis.h | 3 ++-
llvm/lib/MC/MCInstrAnalysis.cpp | 3 +--
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 6 +++---
llvm/tools/llvm-objdump/llvm-objdump.cpp | 3 ++-
4 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/llvm/include/llvm/MC/MCInstrAnalysis.h b/llvm/include/llvm/MC/MCInstrAnalysis.h
index 614f220b283be..a0411a365791a 100644
--- a/llvm/include/llvm/MC/MCInstrAnalysis.h
+++ b/llvm/include/llvm/MC/MCInstrAnalysis.h
@@ -186,7 +186,8 @@ class LLVM_ABI MCInstrAnalysis {
/// Given an instruction that accesses a memory address, try to compute
/// the target address. Return true on success, and the address in \p Target.
virtual bool evaluateInstruction(const MCInst &Inst, uint64_t Addr,
- uint64_t Size, uint64_t &Target, const MCSubtargetInfo &STI) const;
+ uint64_t Size, uint64_t &Target,
+ const MCSubtargetInfo &STI) const;
/// Given an instruction tries to get the address of a memory operand. Returns
/// the address on success.
diff --git a/llvm/lib/MC/MCInstrAnalysis.cpp b/llvm/lib/MC/MCInstrAnalysis.cpp
index 2dc18682eb0e3..d726b1c0eabbe 100644
--- a/llvm/lib/MC/MCInstrAnalysis.cpp
+++ b/llvm/lib/MC/MCInstrAnalysis.cpp
@@ -31,8 +31,7 @@ bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
}
bool MCInstrAnalysis::evaluateInstruction(const MCInst &Inst, uint64_t Addr,
- uint64_t Size,
- uint64_t &Target,
+ uint64_t Size, uint64_t &Target,
const MCSubtargetInfo &STI) const {
return false;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 8912ae5177a94..237d1a2d4de5f 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -244,7 +244,8 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
bool evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target, const MCSubtargetInfo &STI) const override {
+ uint64_t &Target,
+ const MCSubtargetInfo &STI) const override {
unsigned int ArchRegWidth = STI.getTargetTriple().getArchPointerBitWidth();
switch(Inst.getOpcode()) {
default:
@@ -442,7 +443,6 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
// Register the null target streamer.
TargetRegistry::RegisterNullTargetStreamer(*T,
createRISCVNullTargetStreamer);
- TargetRegistry::RegisterMCInstrAnalysis(*T,
- createRISCVInstrAnalysis);
+ TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis);
}
}
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index 3612ce9e30c6a..a51f5a05b0fbb 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -2358,7 +2358,8 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
bool PrintTarget = DT->InstrAnalysis->evaluateBranch(
Inst, SectionAddr + Index, Size, Target) ||
DT->InstrAnalysis->evaluateInstruction(
- Inst, SectionAddr + Index, Size, Target, *DT->SubtargetInfo);
+ Inst, SectionAddr + Index, Size, Target,
+ *DT->SubtargetInfo);
if (!PrintTarget) {
if (std::optional<uint64_t> MaybeTarget =
DT->InstrAnalysis->evaluateMemoryOperandAddress(
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