[llvm] [NVPTX] fold movs into loads and stores (PR #144581)

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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index e736b2ca6..d1c7be34a 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -3493,10 +3493,10 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
         if (P.getNode())
           P.getNode()->setIROrder(Arg.getArgNo() + 1);
         for (const unsigned J : llvm::seq(NumElts)) {
-          SDValue Elt =
-              DAG.getNode(LoadVT.isVector() ? ISD::EXTRACT_SUBVECTOR
-                                            : ISD::EXTRACT_VECTOR_ELT,
-                          dl, LoadVT, P, DAG.getIntPtrConstant(J * PackingAmt, dl));
+          SDValue Elt = DAG.getNode(LoadVT.isVector() ? ISD::EXTRACT_SUBVECTOR
+                                                      : ISD::EXTRACT_VECTOR_ELT,
+                                    dl, LoadVT, P,
+                                    DAG.getIntPtrConstant(J * PackingAmt, dl));
 
           // Extend or truncate the element if necessary (e.g. an i8 is loaded
           // into an i16 register)
@@ -5234,8 +5234,8 @@ static SDValue combinePackingMovIntoStore(SDNode *N,
     Operands.push_back(Op);
 
   // Now we replace the store
-  return DCI.DAG.getMemIntrinsicNode(Opcode, SDLoc(N), N->getVTList(),
-          Operands, MemVT, ST->getMemOperand());
+  return DCI.DAG.getMemIntrinsicNode(Opcode, SDLoc(N), N->getVTList(), Operands,
+                                     MemVT, ST->getMemOperand());
 }
 
 static SDValue PerformStoreCombineHelper(SDNode *N,

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https://github.com/llvm/llvm-project/pull/144581