[llvm] [SelectionDAG][x86] Ensure vector reduction optimization (PR #144231)

[Suhajda Tamás via llvm-commits]

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@@ -1435,6 +1435,20 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
       setOperationAction(ISD::BITREVERSE, VT, Custom);
   }
 
+  // Vector min/max reductions
+  if (Subtarget.hasSSE41())
+  {
+    for (MVT VT : MVT::vector_valuetypes()) {
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sutajo wrote:

X86TTIImpl::shouldExpandReduction does a more thorough check. If we can't lower them properly they will get expanded to shuffles and we will never see these reductions in the DAG.

https://github.com/llvm/llvm-project/pull/144231