[llvm] [RISCV] Set the exact flag on the SRL created for converting vscale to a read of vlenb. (PR #144571)

[Craig Topper via llvm-commits]

topperc wrote:

> We have target known bits set for READ_VLENB, why aren't we able to infer the exact flag on the select from that?  Are we missing some general combine?

DAGCombine basically never infers any flags.

https://github.com/llvm/llvm-project/pull/144571