[llvm] a5f5f12 - [AMDGPU] Use subtarget feature for v_lshl_add_u64 pattern. NFC. (#144544)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 17 08:46:48 PDT 2025
Author: Jay Foad
Date: 2025-06-17T16:46:44+01:00
New Revision: a5f5f1209aa122ee295ae0dc0f1ee594ad988ecd
URL: https://github.com/llvm/llvm-project/commit/a5f5f1209aa122ee295ae0dc0f1ee594ad988ecd
DIFF: https://github.com/llvm/llvm-project/commit/a5f5f1209aa122ee295ae0dc0f1ee594ad988ecd.diff
LOG: [AMDGPU] Use subtarget feature for v_lshl_add_u64 pattern. NFC. (#144544)
Following on from #133723, use the new subtarget feature for the
selection pattern as well as for the instruction definition.
Added:
Modified:
llvm/lib/Target/AMDGPU/VOP3Instructions.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index a005e0245b8ff..f372101cb7b77 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -806,7 +806,7 @@ def : GCNPat<
(DivergentBinFrag<mul> i32:$src0, IsPow2Plus1:$src1),
(V_LSHL_ADD_U32_e64 i32:$src0, (i32 (Log2_32 imm:$src1)), i32:$src0)>;
-let SubtargetPredicate = isGFX940Plus in
+let SubtargetPredicate = HasLshlAddU64Inst in
def : GCNPat<
(ThreeOpFrag<shl_0_to_4, add> i64:$src0, i32:$src1, i64:$src2),
(V_LSHL_ADD_U64_e64 VSrc_b64:$src0, VSrc_b32:$src1, VSrc_b64:$src2)
More information about the llvm-commits
mailing list