[llvm] [AMDGPU] Support D16 folding for image.sample with multiple extractelement and fptrunc users (PR #141758)
Harrison Hao via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 16 23:28:06 PDT 2025
https://github.com/harrisonGPU updated https://github.com/llvm/llvm-project/pull/141758
>From 2d3c84a20222567d3fdfca28861cc6610399f8cf Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Wed, 28 May 2025 16:30:47 +0800
Subject: [PATCH 1/6] [AMDGPU] Support D16 folding for image.sample with
multiple extractelement and fptrunc users
---
.../AMDGPU/AMDGPUInstCombineIntrinsic.cpp | 62 +++
.../InstCombine/AMDGPU/image-d16.ll | 417 +++++++++++++++++-
2 files changed, 477 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
index 9be8821d5bf96..ba8ec79f8e783 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
@@ -269,6 +269,68 @@ simplifyAMDGCNImageIntrinsic(const GCNSubtarget *ST,
ArgTys[0] = User->getType();
});
}
+ } else {
+ // Only perform D16 folding if every user of the image sample is
+ // an ExtractElementInst immediately followed by an FPTrunc to half.
+ SmallVector<ExtractElementInst *, 4> Extracts;
+ SmallVector<FPTruncInst *, 4> Truncs;
+ bool AllHalfExtracts = true;
+
+ for (User *U : II.users()) {
+ auto *Ext = dyn_cast<ExtractElementInst>(U);
+ if (!Ext || !Ext->hasOneUse()) {
+ AllHalfExtracts = false;
+ break;
+ }
+ auto *Tr = dyn_cast<FPTruncInst>(*Ext->user_begin());
+ if (!Tr || !Tr->getType()->getScalarType()->isHalfTy()) {
+ AllHalfExtracts = false;
+ break;
+ }
+ Extracts.push_back(Ext);
+ Truncs.push_back(Tr);
+ }
+
+ if (AllHalfExtracts && !Extracts.empty()) {
+ auto *VecTy = cast<VectorType>(II.getType());
+ unsigned NElts = VecTy->getElementCount().getKnownMinValue();
+ Type *HalfVecTy =
+ VectorType::get(Type::getHalfTy(II.getContext()), NElts, false);
+
+ // Obtain the original image sample intrinsic's signature
+ // and replace its return type with the half-vector for D16 folding
+ SmallVector<Type *, 8> SigTys;
+ if (!Intrinsic::getIntrinsicSignature(II.getCalledFunction(), SigTys))
+ return nullptr;
+ SigTys[0] = HalfVecTy;
+
+ Module *M = II.getModule();
+ Function *HalfDecl =
+ Intrinsic::getOrInsertDeclaration(M, ImageDimIntr->Intr, SigTys);
+
+ II.mutateType(HalfVecTy);
+ II.setCalledFunction(HalfDecl);
+
+ IRBuilder<> Builder(&II);
+ for (auto [lane, Ext] : enumerate(Extracts)) {
+ FPTruncInst *Tr = Truncs[lane];
+ Value *Idx = Ext->getIndexOperand();
+
+ Builder.SetInsertPoint(Tr);
+
+ Value *HalfExtract = Builder.CreateExtractElement(&II, Idx);
+ HalfExtract->takeName(Tr);
+
+ Tr->replaceAllUsesWith(HalfExtract);
+ }
+
+ for (auto *T : Truncs)
+ IC.eraseInstFromFunction(*T);
+ for (auto *E : Extracts)
+ IC.eraseInstFromFunction(*E);
+
+ return &II;
+ }
}
}
}
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll b/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll
index 30431ad724843..d39cceb9b549a 100644
--- a/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll
@@ -1,8 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx700 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX7 %s
; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx810 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX81PLUS %s
-; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx900 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX81PLUS %s
-; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx1010 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX81PLUS %s
+; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx900 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX9 %s
+; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx1010 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX10PLUS %s
+; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx1100 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX11 %s
define amdgpu_ps half @image_sample_2d_fptrunc_to_d16(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
; GFX7-LABEL: @image_sample_2d_fptrunc_to_d16(
@@ -16,6 +17,21 @@ define amdgpu_ps half @image_sample_2d_fptrunc_to_d16(<8 x i32> inreg %rsrc, <4
; GFX81PLUS-NEXT: [[TEX:%.*]] = call half @llvm.amdgcn.image.sample.lz.2d.f16.f32.v8i32.v4i32(i32 1, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
; GFX81PLUS-NEXT: ret half [[TEX]]
;
+; GFX9-LABEL: @image_sample_2d_fptrunc_to_d16(
+; GFX9-NEXT: main_body:
+; GFX9-NEXT: [[TEX:%.*]] = call half @llvm.amdgcn.image.sample.lz.2d.f16.f32.v8i32.v4i32(i32 1, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
+; GFX9-NEXT: ret half [[TEX]]
+;
+; GFX10PLUS-LABEL: @image_sample_2d_fptrunc_to_d16(
+; GFX10PLUS-NEXT: main_body:
+; GFX10PLUS-NEXT: [[TEX:%.*]] = call half @llvm.amdgcn.image.sample.lz.2d.f16.f32.v8i32.v4i32(i32 1, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
+; GFX10PLUS-NEXT: ret half [[TEX]]
+;
+; GFX11-LABEL: @image_sample_2d_fptrunc_to_d16(
+; GFX11-NEXT: main_body:
+; GFX11-NEXT: [[TEX:%.*]] = call half @llvm.amdgcn.image.sample.lz.2d.f16.f32.v8i32.v4i32(i32 1, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
+; GFX11-NEXT: ret half [[TEX]]
+;
main_body:
%tex = call float @llvm.amdgcn.image.sample.lz.2d.f32.f32.v8i32.v4i32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
%tex_half = fptrunc float %tex to half
@@ -40,6 +56,30 @@ define amdgpu_ps half @image_sample_2d_v2f32(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX81PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_0]]
;
+; GFX9-LABEL: @image_sample_2d_v2f32(
+; GFX9-NEXT: main_body:
+; GFX9-NEXT: [[TEX:%.*]] = call <2 x half> @llvm.amdgcn.image.sample.lz.2d.v2f16.f32.v8i32.v4i32(i32 3, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
+; GFX9-NEXT: [[TEX_HALF_0:%.*]] = extractelement <2 x half> [[TEX]], i64 0
+; GFX9-NEXT: [[TEX_HALF_1:%.*]] = extractelement <2 x half> [[TEX]], i64 1
+; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
+; GFX9-NEXT: ret half [[ADDF_SUM_0]]
+;
+; GFX10PLUS-LABEL: @image_sample_2d_v2f32(
+; GFX10PLUS-NEXT: main_body:
+; GFX10PLUS-NEXT: [[TEX:%.*]] = call <2 x half> @llvm.amdgcn.image.sample.lz.2d.v2f16.f32.v8i32.v4i32(i32 3, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
+; GFX10PLUS-NEXT: [[TEX_HALF_0:%.*]] = extractelement <2 x half> [[TEX]], i64 0
+; GFX10PLUS-NEXT: [[TEX_HALF_1:%.*]] = extractelement <2 x half> [[TEX]], i64 1
+; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
+; GFX10PLUS-NEXT: ret half [[ADDF_SUM_0]]
+;
+; GFX11-LABEL: @image_sample_2d_v2f32(
+; GFX11-NEXT: main_body:
+; GFX11-NEXT: [[TEX:%.*]] = call <2 x half> @llvm.amdgcn.image.sample.lz.2d.v2f16.f32.v8i32.v4i32(i32 3, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
+; GFX11-NEXT: [[TEX_HALF_0:%.*]] = extractelement <2 x half> [[TEX]], i64 0
+; GFX11-NEXT: [[TEX_HALF_1:%.*]] = extractelement <2 x half> [[TEX]], i64 1
+; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
+; GFX11-NEXT: ret half [[ADDF_SUM_0]]
+;
main_body:
%tex = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32.v8i32.v4i32(i32 3, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
%tex_2_half = fptrunc <2 x float> %tex to <2 x half>
@@ -71,6 +111,36 @@ define amdgpu_ps half @image_sample_2d_v3f32(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX81PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[ADDF_SUM_0]], [[TEX_HALF_2]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_1]]
;
+; GFX9-LABEL: @image_sample_2d_v3f32(
+; GFX9-NEXT: main_body:
+; GFX9-NEXT: [[TEX:%.*]] = call <3 x half> @llvm.amdgcn.image.sample.lz.2d.v3f16.f32.v8i32.v4i32(i32 7, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
+; GFX9-NEXT: [[TEX_HALF_0:%.*]] = extractelement <3 x half> [[TEX]], i64 0
+; GFX9-NEXT: [[TEX_HALF_1:%.*]] = extractelement <3 x half> [[TEX]], i64 1
+; GFX9-NEXT: [[TEX_HALF_2:%.*]] = extractelement <3 x half> [[TEX]], i64 2
+; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
+; GFX9-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[ADDF_SUM_0]], [[TEX_HALF_2]]
+; GFX9-NEXT: ret half [[ADDF_SUM_1]]
+;
+; GFX10PLUS-LABEL: @image_sample_2d_v3f32(
+; GFX10PLUS-NEXT: main_body:
+; GFX10PLUS-NEXT: [[TEX:%.*]] = call <3 x half> @llvm.amdgcn.image.sample.lz.2d.v3f16.f32.v8i32.v4i32(i32 7, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
+; GFX10PLUS-NEXT: [[TEX_HALF_0:%.*]] = extractelement <3 x half> [[TEX]], i64 0
+; GFX10PLUS-NEXT: [[TEX_HALF_1:%.*]] = extractelement <3 x half> [[TEX]], i64 1
+; GFX10PLUS-NEXT: [[TEX_HALF_2:%.*]] = extractelement <3 x half> [[TEX]], i64 2
+; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
+; GFX10PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[ADDF_SUM_0]], [[TEX_HALF_2]]
+; GFX10PLUS-NEXT: ret half [[ADDF_SUM_1]]
+;
+; GFX11-LABEL: @image_sample_2d_v3f32(
+; GFX11-NEXT: main_body:
+; GFX11-NEXT: [[TEX:%.*]] = call <3 x half> @llvm.amdgcn.image.sample.lz.2d.v3f16.f32.v8i32.v4i32(i32 7, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
+; GFX11-NEXT: [[TEX_HALF_0:%.*]] = extractelement <3 x half> [[TEX]], i64 0
+; GFX11-NEXT: [[TEX_HALF_1:%.*]] = extractelement <3 x half> [[TEX]], i64 1
+; GFX11-NEXT: [[TEX_HALF_2:%.*]] = extractelement <3 x half> [[TEX]], i64 2
+; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
+; GFX11-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[ADDF_SUM_0]], [[TEX_HALF_2]]
+; GFX11-NEXT: ret half [[ADDF_SUM_1]]
+;
main_body:
%tex = call <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32.v8i32.v4i32(i32 7, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
%tex_3_half = fptrunc <3 x float> %tex to <3 x half>
@@ -108,6 +178,42 @@ define amdgpu_ps half @image_sample_2d_v4f32(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX81PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_2]]
;
+; GFX9-LABEL: @image_sample_2d_v4f32(
+; GFX9-NEXT: main_body:
+; GFX9-NEXT: [[TEX:%.*]] = call <4 x half> @llvm.amdgcn.image.sample.lz.2d.v4f16.f32.v8i32.v4i32(i32 15, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
+; GFX9-NEXT: [[TEX_HALF_0:%.*]] = extractelement <4 x half> [[TEX]], i64 0
+; GFX9-NEXT: [[TEX_HALF_1:%.*]] = extractelement <4 x half> [[TEX]], i64 1
+; GFX9-NEXT: [[TEX_HALF_2:%.*]] = extractelement <4 x half> [[TEX]], i64 2
+; GFX9-NEXT: [[TEX_HALF_3:%.*]] = extractelement <4 x half> [[TEX]], i64 3
+; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
+; GFX9-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[TEX_HALF_2]], [[TEX_HALF_3]]
+; GFX9-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
+; GFX9-NEXT: ret half [[ADDF_SUM_2]]
+;
+; GFX10PLUS-LABEL: @image_sample_2d_v4f32(
+; GFX10PLUS-NEXT: main_body:
+; GFX10PLUS-NEXT: [[TEX:%.*]] = call <4 x half> @llvm.amdgcn.image.sample.lz.2d.v4f16.f32.v8i32.v4i32(i32 15, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
+; GFX10PLUS-NEXT: [[TEX_HALF_0:%.*]] = extractelement <4 x half> [[TEX]], i64 0
+; GFX10PLUS-NEXT: [[TEX_HALF_1:%.*]] = extractelement <4 x half> [[TEX]], i64 1
+; GFX10PLUS-NEXT: [[TEX_HALF_2:%.*]] = extractelement <4 x half> [[TEX]], i64 2
+; GFX10PLUS-NEXT: [[TEX_HALF_3:%.*]] = extractelement <4 x half> [[TEX]], i64 3
+; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
+; GFX10PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[TEX_HALF_2]], [[TEX_HALF_3]]
+; GFX10PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
+; GFX10PLUS-NEXT: ret half [[ADDF_SUM_2]]
+;
+; GFX11-LABEL: @image_sample_2d_v4f32(
+; GFX11-NEXT: main_body:
+; GFX11-NEXT: [[TEX:%.*]] = call <4 x half> @llvm.amdgcn.image.sample.lz.2d.v4f16.f32.v8i32.v4i32(i32 15, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
+; GFX11-NEXT: [[TEX_HALF_0:%.*]] = extractelement <4 x half> [[TEX]], i64 0
+; GFX11-NEXT: [[TEX_HALF_1:%.*]] = extractelement <4 x half> [[TEX]], i64 1
+; GFX11-NEXT: [[TEX_HALF_2:%.*]] = extractelement <4 x half> [[TEX]], i64 2
+; GFX11-NEXT: [[TEX_HALF_3:%.*]] = extractelement <4 x half> [[TEX]], i64 3
+; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
+; GFX11-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[TEX_HALF_2]], [[TEX_HALF_3]]
+; GFX11-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
+; GFX11-NEXT: ret half [[ADDF_SUM_2]]
+;
main_body:
%tex = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
%tex_4_half = fptrunc <4 x float> %tex to <4 x half>
@@ -121,6 +227,79 @@ main_body:
ret half %addf_sum.2
}
+define void @image_sample_2d_multi_fptrunc_to_d16(<8 x i32> %surf_desc, <4 x i32> %samp, float %u, float %v, ptr addrspace(7) %out) {
+; GFX7-LABEL: @image_sample_2d_multi_fptrunc_to_d16(
+; GFX7-NEXT: main_body:
+; GFX7-NEXT: [[SAMPLE:%.*]] = call <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)
+; GFX7-NEXT: [[E0:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 0
+; GFX7-NEXT: [[H0:%.*]] = fptrunc float [[E0]] to half
+; GFX7-NEXT: [[E1:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 1
+; GFX7-NEXT: [[H1:%.*]] = fptrunc float [[E1]] to half
+; GFX7-NEXT: [[E2:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 2
+; GFX7-NEXT: [[H2:%.*]] = fptrunc float [[E2]] to half
+; GFX7-NEXT: [[MUL:%.*]] = fmul half [[H0]], [[H1]]
+; GFX7-NEXT: [[RES:%.*]] = fadd half [[MUL]], [[H2]]
+; GFX7-NEXT: store half [[RES]], ptr addrspace(7) [[OUT:%.*]], align 2
+; GFX7-NEXT: ret void
+;
+; GFX81PLUS-LABEL: @image_sample_2d_multi_fptrunc_to_d16(
+; GFX81PLUS-NEXT: main_body:
+; GFX81PLUS-NEXT: [[SAMPLE:%.*]] = call <3 x half> @llvm.amdgcn.image.sample.lz.2d.v3f16.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)
+; GFX81PLUS-NEXT: [[H0:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 0
+; GFX81PLUS-NEXT: [[H1:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 1
+; GFX81PLUS-NEXT: [[H2:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 2
+; GFX81PLUS-NEXT: [[MUL:%.*]] = fmul half [[H0]], [[H1]]
+; GFX81PLUS-NEXT: [[RES:%.*]] = fadd half [[MUL]], [[H2]]
+; GFX81PLUS-NEXT: store half [[RES]], ptr addrspace(7) [[OUT:%.*]], align 2
+; GFX81PLUS-NEXT: ret void
+;
+; GFX9-LABEL: @image_sample_2d_multi_fptrunc_to_d16(
+; GFX9-NEXT: main_body:
+; GFX9-NEXT: [[SAMPLE:%.*]] = call <3 x half> @llvm.amdgcn.image.sample.lz.2d.v3f16.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)
+; GFX9-NEXT: [[HALF_EXT2:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 0
+; GFX9-NEXT: [[HALF_EXT1:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 1
+; GFX9-NEXT: [[HALF_EXT:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 2
+; GFX9-NEXT: [[MUL:%.*]] = fmul half [[HALF_EXT2]], [[HALF_EXT1]]
+; GFX9-NEXT: [[RES:%.*]] = fadd half [[MUL]], [[HALF_EXT]]
+; GFX9-NEXT: store half [[RES]], ptr addrspace(7) [[OUT:%.*]], align 2
+; GFX9-NEXT: ret void
+;
+; GFX10PLUS-LABEL: @image_sample_2d_multi_fptrunc_to_d16(
+; GFX10PLUS-NEXT: main_body:
+; GFX10PLUS-NEXT: [[SAMPLE:%.*]] = call <3 x half> @llvm.amdgcn.image.sample.lz.2d.v3f16.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)
+; GFX10PLUS-NEXT: [[HALF_EXT2:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 0
+; GFX10PLUS-NEXT: [[HALF_EXT1:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 1
+; GFX10PLUS-NEXT: [[HALF_EXT:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 2
+; GFX10PLUS-NEXT: [[MUL:%.*]] = fmul half [[HALF_EXT2]], [[HALF_EXT1]]
+; GFX10PLUS-NEXT: [[RES:%.*]] = fadd half [[MUL]], [[HALF_EXT]]
+; GFX10PLUS-NEXT: store half [[RES]], ptr addrspace(7) [[OUT:%.*]], align 2
+; GFX10PLUS-NEXT: ret void
+;
+; GFX11-LABEL: @image_sample_2d_multi_fptrunc_to_d16(
+; GFX11-NEXT: main_body:
+; GFX11-NEXT: [[SAMPLE:%.*]] = call <3 x half> @llvm.amdgcn.image.sample.lz.2d.v3f16.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)
+; GFX11-NEXT: [[HALF_EXT2:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 0
+; GFX11-NEXT: [[HALF_EXT1:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 1
+; GFX11-NEXT: [[HALF_EXT:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 2
+; GFX11-NEXT: [[MUL:%.*]] = fmul half [[HALF_EXT2]], [[HALF_EXT1]]
+; GFX11-NEXT: [[RES:%.*]] = fadd half [[MUL]], [[HALF_EXT]]
+; GFX11-NEXT: store half [[RES]], ptr addrspace(7) [[OUT:%.*]], align 2
+; GFX11-NEXT: ret void
+;
+main_body:
+ %sample = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float %u, float %v, <8 x i32> %surf_desc, <4 x i32> %samp, i1 false, i32 0, i32 0)
+ %e0 = extractelement <4 x float> %sample, i32 0
+ %h0 = fptrunc float %e0 to half
+ %e1 = extractelement <4 x float> %sample, i32 1
+ %h1 = fptrunc float %e1 to half
+ %e2 = extractelement <4 x float> %sample, i32 2
+ %h2 = fptrunc float %e2 to half
+ %mul = fmul half %h0, %h1
+ %res = fadd half %mul, %h2
+ store half %res, ptr addrspace(7) %out, align 2
+ ret void
+}
+
define amdgpu_ps half @image_gather4_2d_v4f32(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {
; GFX7-LABEL: @image_gather4_2d_v4f32(
; GFX7-NEXT: main_body:
@@ -147,6 +326,42 @@ define amdgpu_ps half @image_gather4_2d_v4f32(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX81PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_2]]
;
+; GFX9-LABEL: @image_gather4_2d_v4f32(
+; GFX9-NEXT: main_body:
+; GFX9-NEXT: [[TEX:%.*]] = call <4 x half> @llvm.amdgcn.image.gather4.2d.v4f16.f16.v8i32.v4i32(i32 1, half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
+; GFX9-NEXT: [[TEX_HALF_0:%.*]] = extractelement <4 x half> [[TEX]], i64 0
+; GFX9-NEXT: [[TEX_HALF_1:%.*]] = extractelement <4 x half> [[TEX]], i64 1
+; GFX9-NEXT: [[TEX_HALF_2:%.*]] = extractelement <4 x half> [[TEX]], i64 2
+; GFX9-NEXT: [[TEX_HALF_3:%.*]] = extractelement <4 x half> [[TEX]], i64 3
+; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
+; GFX9-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[TEX_HALF_2]], [[TEX_HALF_3]]
+; GFX9-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
+; GFX9-NEXT: ret half [[ADDF_SUM_2]]
+;
+; GFX10PLUS-LABEL: @image_gather4_2d_v4f32(
+; GFX10PLUS-NEXT: main_body:
+; GFX10PLUS-NEXT: [[TEX:%.*]] = call <4 x half> @llvm.amdgcn.image.gather4.2d.v4f16.f16.v8i32.v4i32(i32 1, half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
+; GFX10PLUS-NEXT: [[TEX_HALF_0:%.*]] = extractelement <4 x half> [[TEX]], i64 0
+; GFX10PLUS-NEXT: [[TEX_HALF_1:%.*]] = extractelement <4 x half> [[TEX]], i64 1
+; GFX10PLUS-NEXT: [[TEX_HALF_2:%.*]] = extractelement <4 x half> [[TEX]], i64 2
+; GFX10PLUS-NEXT: [[TEX_HALF_3:%.*]] = extractelement <4 x half> [[TEX]], i64 3
+; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
+; GFX10PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[TEX_HALF_2]], [[TEX_HALF_3]]
+; GFX10PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
+; GFX10PLUS-NEXT: ret half [[ADDF_SUM_2]]
+;
+; GFX11-LABEL: @image_gather4_2d_v4f32(
+; GFX11-NEXT: main_body:
+; GFX11-NEXT: [[TEX:%.*]] = call <4 x half> @llvm.amdgcn.image.gather4.2d.v4f16.f16.v8i32.v4i32(i32 1, half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
+; GFX11-NEXT: [[TEX_HALF_0:%.*]] = extractelement <4 x half> [[TEX]], i64 0
+; GFX11-NEXT: [[TEX_HALF_1:%.*]] = extractelement <4 x half> [[TEX]], i64 1
+; GFX11-NEXT: [[TEX_HALF_2:%.*]] = extractelement <4 x half> [[TEX]], i64 2
+; GFX11-NEXT: [[TEX_HALF_3:%.*]] = extractelement <4 x half> [[TEX]], i64 3
+; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
+; GFX11-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[TEX_HALF_2]], [[TEX_HALF_3]]
+; GFX11-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
+; GFX11-NEXT: ret half [[ADDF_SUM_2]]
+;
main_body:
%tex = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f16.v8i32.v4i32(i32 1, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
%tex_4_half = fptrunc <4 x float> %tex to <4 x half>
@@ -169,6 +384,18 @@ define amdgpu_ps half @load_1d(i16 %s, <8 x i32> inreg %rsrc) {
; GFX81PLUS-LABEL: @load_1d(
; GFX81PLUS-NEXT: [[S_FLOAT:%.*]] = call half @llvm.amdgcn.image.load.1d.f16.i16.v8i32(i32 1, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
; GFX81PLUS-NEXT: ret half [[S_FLOAT]]
+;
+; GFX9-LABEL: @load_1d(
+; GFX9-NEXT: [[S_FLOAT:%.*]] = call half @llvm.amdgcn.image.load.1d.f16.i16.v8i32(i32 1, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX9-NEXT: ret half [[S_FLOAT]]
+;
+; GFX10PLUS-LABEL: @load_1d(
+; GFX10PLUS-NEXT: [[S_FLOAT:%.*]] = call half @llvm.amdgcn.image.load.1d.f16.i16.v8i32(i32 1, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX10PLUS-NEXT: ret half [[S_FLOAT]]
+;
+; GFX11-LABEL: @load_1d(
+; GFX11-NEXT: [[S_FLOAT:%.*]] = call half @llvm.amdgcn.image.load.1d.f16.i16.v8i32(i32 1, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX11-NEXT: ret half [[S_FLOAT]]
;
%s_float = call float @llvm.amdgcn.image.load.1d.f32.i16.v8i32(i32 1, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
%s_half = fptrunc float %s_float to half
@@ -190,6 +417,27 @@ define amdgpu_ps half @load_1d_v2(i16 %s, <8 x i32> inreg %rsrc) {
; GFX81PLUS-NEXT: [[S1:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 1
; GFX81PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_0]]
+;
+; GFX9-LABEL: @load_1d_v2(
+; GFX9-NEXT: [[V2_FLOAT:%.*]] = call <2 x half> @llvm.amdgcn.image.load.1d.v2f16.i16.v8i32(i32 3, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX9-NEXT: [[S0:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 0
+; GFX9-NEXT: [[S1:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 1
+; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
+; GFX9-NEXT: ret half [[ADDF_SUM_0]]
+;
+; GFX10PLUS-LABEL: @load_1d_v2(
+; GFX10PLUS-NEXT: [[V2_FLOAT:%.*]] = call <2 x half> @llvm.amdgcn.image.load.1d.v2f16.i16.v8i32(i32 3, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX10PLUS-NEXT: [[S0:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 0
+; GFX10PLUS-NEXT: [[S1:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 1
+; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
+; GFX10PLUS-NEXT: ret half [[ADDF_SUM_0]]
+;
+; GFX11-LABEL: @load_1d_v2(
+; GFX11-NEXT: [[V2_FLOAT:%.*]] = call <2 x half> @llvm.amdgcn.image.load.1d.v2f16.i16.v8i32(i32 3, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX11-NEXT: [[S0:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 0
+; GFX11-NEXT: [[S1:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 1
+; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
+; GFX11-NEXT: ret half [[ADDF_SUM_0]]
;
%v2_float = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i16.v8i32(i32 3, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
%v2_half = fptrunc <2 x float> %v2_float to <2 x half>
@@ -218,6 +466,33 @@ define amdgpu_ps half @load_1d_v3(i16 %s, <8 x i32> inreg %rsrc) {
; GFX81PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
; GFX81PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_1]]
+;
+; GFX9-LABEL: @load_1d_v3(
+; GFX9-NEXT: [[V3_FLOAT:%.*]] = call <3 x half> @llvm.amdgcn.image.load.1d.v3f16.i16.v8i32(i32 7, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX9-NEXT: [[S0:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 0
+; GFX9-NEXT: [[S1:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 1
+; GFX9-NEXT: [[S2:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 2
+; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
+; GFX9-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]
+; GFX9-NEXT: ret half [[ADDF_SUM_1]]
+;
+; GFX10PLUS-LABEL: @load_1d_v3(
+; GFX10PLUS-NEXT: [[V3_FLOAT:%.*]] = call <3 x half> @llvm.amdgcn.image.load.1d.v3f16.i16.v8i32(i32 7, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX10PLUS-NEXT: [[S0:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 0
+; GFX10PLUS-NEXT: [[S1:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 1
+; GFX10PLUS-NEXT: [[S2:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 2
+; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
+; GFX10PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]
+; GFX10PLUS-NEXT: ret half [[ADDF_SUM_1]]
+;
+; GFX11-LABEL: @load_1d_v3(
+; GFX11-NEXT: [[V3_FLOAT:%.*]] = call <3 x half> @llvm.amdgcn.image.load.1d.v3f16.i16.v8i32(i32 7, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX11-NEXT: [[S0:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 0
+; GFX11-NEXT: [[S1:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 1
+; GFX11-NEXT: [[S2:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 2
+; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
+; GFX11-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]
+; GFX11-NEXT: ret half [[ADDF_SUM_1]]
;
%v3_float = call <3 x float> @llvm.amdgcn.image.load.1d.v3f32.i16.v8i32(i32 7, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
%v3_half = fptrunc <3 x float> %v3_float to <3 x half>
@@ -252,6 +527,39 @@ define amdgpu_ps half @load_1d_v4(i16 %s, <8 x i32> inreg %rsrc) {
; GFX81PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[S3]]
; GFX81PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_2]]
+;
+; GFX9-LABEL: @load_1d_v4(
+; GFX9-NEXT: [[V4_FLOAT:%.*]] = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16.v8i32(i32 15, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX9-NEXT: [[S0:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 0
+; GFX9-NEXT: [[S1:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 1
+; GFX9-NEXT: [[S2:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 2
+; GFX9-NEXT: [[S3:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 3
+; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
+; GFX9-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[S3]]
+; GFX9-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
+; GFX9-NEXT: ret half [[ADDF_SUM_2]]
+;
+; GFX10PLUS-LABEL: @load_1d_v4(
+; GFX10PLUS-NEXT: [[V4_FLOAT:%.*]] = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16.v8i32(i32 15, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX10PLUS-NEXT: [[S0:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 0
+; GFX10PLUS-NEXT: [[S1:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 1
+; GFX10PLUS-NEXT: [[S2:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 2
+; GFX10PLUS-NEXT: [[S3:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 3
+; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
+; GFX10PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[S3]]
+; GFX10PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
+; GFX10PLUS-NEXT: ret half [[ADDF_SUM_2]]
+;
+; GFX11-LABEL: @load_1d_v4(
+; GFX11-NEXT: [[V4_FLOAT:%.*]] = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16.v8i32(i32 15, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX11-NEXT: [[S0:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 0
+; GFX11-NEXT: [[S1:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 1
+; GFX11-NEXT: [[S2:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 2
+; GFX11-NEXT: [[S3:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 3
+; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
+; GFX11-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[S3]]
+; GFX11-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
+; GFX11-NEXT: ret half [[ADDF_SUM_2]]
;
%v4_float = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16.v8i32(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
%v4_half = fptrunc <4 x float> %v4_float to <4 x half>
@@ -277,6 +585,21 @@ define amdgpu_ps half @load_2dmsaa(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %f
; GFX81PLUS-NEXT: [[S_FLOAT:%.*]] = call half @llvm.amdgcn.image.msaa.load.x.2dmsaa.f16.i32.v8i32(i32 1, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
; GFX81PLUS-NEXT: ret half [[S_FLOAT]]
;
+; GFX9-LABEL: @load_2dmsaa(
+; GFX9-NEXT: main_body:
+; GFX9-NEXT: [[S_FLOAT:%.*]] = call half @llvm.amdgcn.image.msaa.load.x.2dmsaa.f16.i32.v8i32(i32 1, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX9-NEXT: ret half [[S_FLOAT]]
+;
+; GFX10PLUS-LABEL: @load_2dmsaa(
+; GFX10PLUS-NEXT: main_body:
+; GFX10PLUS-NEXT: [[S_FLOAT:%.*]] = call half @llvm.amdgcn.image.msaa.load.x.2dmsaa.f16.i32.v8i32(i32 1, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX10PLUS-NEXT: ret half [[S_FLOAT]]
+;
+; GFX11-LABEL: @load_2dmsaa(
+; GFX11-NEXT: main_body:
+; GFX11-NEXT: [[S_FLOAT:%.*]] = call half @llvm.amdgcn.image.msaa.load.x.2dmsaa.f16.i32.v8i32(i32 1, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX11-NEXT: ret half [[S_FLOAT]]
+;
main_body:
%s_float = call float @llvm.amdgcn.image.msaa.load.x.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
%s_half = fptrunc float %s_float to half
@@ -301,6 +624,30 @@ define amdgpu_ps half @load_2dmsaa_v2(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32
; GFX81PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_0]]
;
+; GFX9-LABEL: @load_2dmsaa_v2(
+; GFX9-NEXT: main_body:
+; GFX9-NEXT: [[V2_FLOAT:%.*]] = call <2 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v2f16.i32.v8i32(i32 3, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX9-NEXT: [[S0:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 0
+; GFX9-NEXT: [[S1:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 1
+; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
+; GFX9-NEXT: ret half [[ADDF_SUM_0]]
+;
+; GFX10PLUS-LABEL: @load_2dmsaa_v2(
+; GFX10PLUS-NEXT: main_body:
+; GFX10PLUS-NEXT: [[V2_FLOAT:%.*]] = call <2 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v2f16.i32.v8i32(i32 3, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX10PLUS-NEXT: [[S0:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 0
+; GFX10PLUS-NEXT: [[S1:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 1
+; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
+; GFX10PLUS-NEXT: ret half [[ADDF_SUM_0]]
+;
+; GFX11-LABEL: @load_2dmsaa_v2(
+; GFX11-NEXT: main_body:
+; GFX11-NEXT: [[V2_FLOAT:%.*]] = call <2 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v2f16.i32.v8i32(i32 3, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX11-NEXT: [[S0:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 0
+; GFX11-NEXT: [[S1:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 1
+; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
+; GFX11-NEXT: ret half [[ADDF_SUM_0]]
+;
main_body:
%v2_float = call <2 x float> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v2f32.i32.v8i32(i32 3, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
%v2_half = fptrunc <2 x float> %v2_float to <2 x half>
@@ -332,6 +679,36 @@ define amdgpu_ps half @load_2dmsaa_v3(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32
; GFX81PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_1]]
;
+; GFX9-LABEL: @load_2dmsaa_v3(
+; GFX9-NEXT: main_body:
+; GFX9-NEXT: [[V3_FLOAT:%.*]] = call <3 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v3f16.i32.v8i32(i32 7, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX9-NEXT: [[S0:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 0
+; GFX9-NEXT: [[S1:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 1
+; GFX9-NEXT: [[S2:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 2
+; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
+; GFX9-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]
+; GFX9-NEXT: ret half [[ADDF_SUM_1]]
+;
+; GFX10PLUS-LABEL: @load_2dmsaa_v3(
+; GFX10PLUS-NEXT: main_body:
+; GFX10PLUS-NEXT: [[V3_FLOAT:%.*]] = call <3 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v3f16.i32.v8i32(i32 7, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX10PLUS-NEXT: [[S0:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 0
+; GFX10PLUS-NEXT: [[S1:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 1
+; GFX10PLUS-NEXT: [[S2:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 2
+; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
+; GFX10PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]
+; GFX10PLUS-NEXT: ret half [[ADDF_SUM_1]]
+;
+; GFX11-LABEL: @load_2dmsaa_v3(
+; GFX11-NEXT: main_body:
+; GFX11-NEXT: [[V3_FLOAT:%.*]] = call <3 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v3f16.i32.v8i32(i32 7, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX11-NEXT: [[S0:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 0
+; GFX11-NEXT: [[S1:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 1
+; GFX11-NEXT: [[S2:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 2
+; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
+; GFX11-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]
+; GFX11-NEXT: ret half [[ADDF_SUM_1]]
+;
main_body:
%v3_float = call <3 x float> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v3f32.i32.v8i32(i32 7, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
%v3_half = fptrunc <3 x float> %v3_float to <3 x half>
@@ -369,6 +746,42 @@ define amdgpu_ps half @load_2dmsaa_v4(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32
; GFX81PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_2]]
;
+; GFX9-LABEL: @load_2dmsaa_v4(
+; GFX9-NEXT: main_body:
+; GFX9-NEXT: [[V4_FLOAT:%.*]] = call <4 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v4f16.i32.v8i32(i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX9-NEXT: [[S0:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 0
+; GFX9-NEXT: [[S1:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 1
+; GFX9-NEXT: [[S2:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 2
+; GFX9-NEXT: [[S3:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 3
+; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
+; GFX9-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[S3]]
+; GFX9-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
+; GFX9-NEXT: ret half [[ADDF_SUM_2]]
+;
+; GFX10PLUS-LABEL: @load_2dmsaa_v4(
+; GFX10PLUS-NEXT: main_body:
+; GFX10PLUS-NEXT: [[V4_FLOAT:%.*]] = call <4 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v4f16.i32.v8i32(i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX10PLUS-NEXT: [[S0:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 0
+; GFX10PLUS-NEXT: [[S1:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 1
+; GFX10PLUS-NEXT: [[S2:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 2
+; GFX10PLUS-NEXT: [[S3:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 3
+; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
+; GFX10PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[S3]]
+; GFX10PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
+; GFX10PLUS-NEXT: ret half [[ADDF_SUM_2]]
+;
+; GFX11-LABEL: @load_2dmsaa_v4(
+; GFX11-NEXT: main_body:
+; GFX11-NEXT: [[V4_FLOAT:%.*]] = call <4 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v4f16.i32.v8i32(i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
+; GFX11-NEXT: [[S0:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 0
+; GFX11-NEXT: [[S1:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 1
+; GFX11-NEXT: [[S2:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 2
+; GFX11-NEXT: [[S3:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 3
+; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
+; GFX11-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[S3]]
+; GFX11-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
+; GFX11-NEXT: ret half [[ADDF_SUM_2]]
+;
main_body:
%v4_float = call <4 x float> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v4f32.i32.v8i32(i32 15, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
%v4_half = fptrunc <4 x float> %v4_float to <4 x half>
>From ac7dc81a93aa13f82b54825830306e72cb28ed2b Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Wed, 28 May 2025 17:03:06 +0000
Subject: [PATCH 2/6] [AMDGPU] Update for comments.
---
.../AMDGPU/AMDGPUInstCombineIntrinsic.cpp | 17 +-
.../InstCombine/AMDGPU/image-d16.ll | 382 +-----------------
2 files changed, 12 insertions(+), 387 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
index ba8ec79f8e783..998f96870a667 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
@@ -283,7 +283,7 @@ simplifyAMDGCNImageIntrinsic(const GCNSubtarget *ST,
break;
}
auto *Tr = dyn_cast<FPTruncInst>(*Ext->user_begin());
- if (!Tr || !Tr->getType()->getScalarType()->isHalfTy()) {
+ if (!Tr || !Tr->getType()->isHalfTy()) {
AllHalfExtracts = false;
break;
}
@@ -293,15 +293,13 @@ simplifyAMDGCNImageIntrinsic(const GCNSubtarget *ST,
if (AllHalfExtracts && !Extracts.empty()) {
auto *VecTy = cast<VectorType>(II.getType());
- unsigned NElts = VecTy->getElementCount().getKnownMinValue();
Type *HalfVecTy =
- VectorType::get(Type::getHalfTy(II.getContext()), NElts, false);
+ VecTy->getWithNewType(Type::getHalfTy(II.getContext()));
// Obtain the original image sample intrinsic's signature
// and replace its return type with the half-vector for D16 folding
SmallVector<Type *, 8> SigTys;
- if (!Intrinsic::getIntrinsicSignature(II.getCalledFunction(), SigTys))
- return nullptr;
+ Intrinsic::getIntrinsicSignature(II.getCalledFunction(), SigTys);
SigTys[0] = HalfVecTy;
Module *M = II.getModule();
@@ -311,9 +309,8 @@ simplifyAMDGCNImageIntrinsic(const GCNSubtarget *ST,
II.mutateType(HalfVecTy);
II.setCalledFunction(HalfDecl);
- IRBuilder<> Builder(&II);
- for (auto [lane, Ext] : enumerate(Extracts)) {
- FPTruncInst *Tr = Truncs[lane];
+ IRBuilder<> Builder(II.getContext());
+ for (auto [Ext, Tr] : zip(Extracts, Truncs)) {
Value *Idx = Ext->getIndexOperand();
Builder.SetInsertPoint(Tr);
@@ -324,9 +321,9 @@ simplifyAMDGCNImageIntrinsic(const GCNSubtarget *ST,
Tr->replaceAllUsesWith(HalfExtract);
}
- for (auto *T : Truncs)
+ for (FPTruncInst *T : Truncs)
IC.eraseInstFromFunction(*T);
- for (auto *E : Extracts)
+ for (ExtractElementInst *E : Extracts)
IC.eraseInstFromFunction(*E);
return &II;
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll b/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll
index d39cceb9b549a..27876b7dbc1e6 100644
--- a/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx700 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX7 %s
; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx810 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX81PLUS %s
-; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx900 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX9 %s
-; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx1010 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX10PLUS %s
-; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx1100 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX11 %s
+; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx900 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX81PLUS %s
+; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx1010 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX81PLUS %s
+; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx1100 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX81PLUS %s
define amdgpu_ps half @image_sample_2d_fptrunc_to_d16(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
; GFX7-LABEL: @image_sample_2d_fptrunc_to_d16(
@@ -17,21 +17,6 @@ define amdgpu_ps half @image_sample_2d_fptrunc_to_d16(<8 x i32> inreg %rsrc, <4
; GFX81PLUS-NEXT: [[TEX:%.*]] = call half @llvm.amdgcn.image.sample.lz.2d.f16.f32.v8i32.v4i32(i32 1, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
; GFX81PLUS-NEXT: ret half [[TEX]]
;
-; GFX9-LABEL: @image_sample_2d_fptrunc_to_d16(
-; GFX9-NEXT: main_body:
-; GFX9-NEXT: [[TEX:%.*]] = call half @llvm.amdgcn.image.sample.lz.2d.f16.f32.v8i32.v4i32(i32 1, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
-; GFX9-NEXT: ret half [[TEX]]
-;
-; GFX10PLUS-LABEL: @image_sample_2d_fptrunc_to_d16(
-; GFX10PLUS-NEXT: main_body:
-; GFX10PLUS-NEXT: [[TEX:%.*]] = call half @llvm.amdgcn.image.sample.lz.2d.f16.f32.v8i32.v4i32(i32 1, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
-; GFX10PLUS-NEXT: ret half [[TEX]]
-;
-; GFX11-LABEL: @image_sample_2d_fptrunc_to_d16(
-; GFX11-NEXT: main_body:
-; GFX11-NEXT: [[TEX:%.*]] = call half @llvm.amdgcn.image.sample.lz.2d.f16.f32.v8i32.v4i32(i32 1, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
-; GFX11-NEXT: ret half [[TEX]]
-;
main_body:
%tex = call float @llvm.amdgcn.image.sample.lz.2d.f32.f32.v8i32.v4i32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
%tex_half = fptrunc float %tex to half
@@ -56,30 +41,6 @@ define amdgpu_ps half @image_sample_2d_v2f32(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX81PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_0]]
;
-; GFX9-LABEL: @image_sample_2d_v2f32(
-; GFX9-NEXT: main_body:
-; GFX9-NEXT: [[TEX:%.*]] = call <2 x half> @llvm.amdgcn.image.sample.lz.2d.v2f16.f32.v8i32.v4i32(i32 3, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
-; GFX9-NEXT: [[TEX_HALF_0:%.*]] = extractelement <2 x half> [[TEX]], i64 0
-; GFX9-NEXT: [[TEX_HALF_1:%.*]] = extractelement <2 x half> [[TEX]], i64 1
-; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
-; GFX9-NEXT: ret half [[ADDF_SUM_0]]
-;
-; GFX10PLUS-LABEL: @image_sample_2d_v2f32(
-; GFX10PLUS-NEXT: main_body:
-; GFX10PLUS-NEXT: [[TEX:%.*]] = call <2 x half> @llvm.amdgcn.image.sample.lz.2d.v2f16.f32.v8i32.v4i32(i32 3, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
-; GFX10PLUS-NEXT: [[TEX_HALF_0:%.*]] = extractelement <2 x half> [[TEX]], i64 0
-; GFX10PLUS-NEXT: [[TEX_HALF_1:%.*]] = extractelement <2 x half> [[TEX]], i64 1
-; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
-; GFX10PLUS-NEXT: ret half [[ADDF_SUM_0]]
-;
-; GFX11-LABEL: @image_sample_2d_v2f32(
-; GFX11-NEXT: main_body:
-; GFX11-NEXT: [[TEX:%.*]] = call <2 x half> @llvm.amdgcn.image.sample.lz.2d.v2f16.f32.v8i32.v4i32(i32 3, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
-; GFX11-NEXT: [[TEX_HALF_0:%.*]] = extractelement <2 x half> [[TEX]], i64 0
-; GFX11-NEXT: [[TEX_HALF_1:%.*]] = extractelement <2 x half> [[TEX]], i64 1
-; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
-; GFX11-NEXT: ret half [[ADDF_SUM_0]]
-;
main_body:
%tex = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32.v8i32.v4i32(i32 3, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
%tex_2_half = fptrunc <2 x float> %tex to <2 x half>
@@ -111,36 +72,6 @@ define amdgpu_ps half @image_sample_2d_v3f32(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX81PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[ADDF_SUM_0]], [[TEX_HALF_2]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_1]]
;
-; GFX9-LABEL: @image_sample_2d_v3f32(
-; GFX9-NEXT: main_body:
-; GFX9-NEXT: [[TEX:%.*]] = call <3 x half> @llvm.amdgcn.image.sample.lz.2d.v3f16.f32.v8i32.v4i32(i32 7, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
-; GFX9-NEXT: [[TEX_HALF_0:%.*]] = extractelement <3 x half> [[TEX]], i64 0
-; GFX9-NEXT: [[TEX_HALF_1:%.*]] = extractelement <3 x half> [[TEX]], i64 1
-; GFX9-NEXT: [[TEX_HALF_2:%.*]] = extractelement <3 x half> [[TEX]], i64 2
-; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
-; GFX9-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[ADDF_SUM_0]], [[TEX_HALF_2]]
-; GFX9-NEXT: ret half [[ADDF_SUM_1]]
-;
-; GFX10PLUS-LABEL: @image_sample_2d_v3f32(
-; GFX10PLUS-NEXT: main_body:
-; GFX10PLUS-NEXT: [[TEX:%.*]] = call <3 x half> @llvm.amdgcn.image.sample.lz.2d.v3f16.f32.v8i32.v4i32(i32 7, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
-; GFX10PLUS-NEXT: [[TEX_HALF_0:%.*]] = extractelement <3 x half> [[TEX]], i64 0
-; GFX10PLUS-NEXT: [[TEX_HALF_1:%.*]] = extractelement <3 x half> [[TEX]], i64 1
-; GFX10PLUS-NEXT: [[TEX_HALF_2:%.*]] = extractelement <3 x half> [[TEX]], i64 2
-; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
-; GFX10PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[ADDF_SUM_0]], [[TEX_HALF_2]]
-; GFX10PLUS-NEXT: ret half [[ADDF_SUM_1]]
-;
-; GFX11-LABEL: @image_sample_2d_v3f32(
-; GFX11-NEXT: main_body:
-; GFX11-NEXT: [[TEX:%.*]] = call <3 x half> @llvm.amdgcn.image.sample.lz.2d.v3f16.f32.v8i32.v4i32(i32 7, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
-; GFX11-NEXT: [[TEX_HALF_0:%.*]] = extractelement <3 x half> [[TEX]], i64 0
-; GFX11-NEXT: [[TEX_HALF_1:%.*]] = extractelement <3 x half> [[TEX]], i64 1
-; GFX11-NEXT: [[TEX_HALF_2:%.*]] = extractelement <3 x half> [[TEX]], i64 2
-; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
-; GFX11-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[ADDF_SUM_0]], [[TEX_HALF_2]]
-; GFX11-NEXT: ret half [[ADDF_SUM_1]]
-;
main_body:
%tex = call <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32.v8i32.v4i32(i32 7, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
%tex_3_half = fptrunc <3 x float> %tex to <3 x half>
@@ -178,42 +109,6 @@ define amdgpu_ps half @image_sample_2d_v4f32(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX81PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_2]]
;
-; GFX9-LABEL: @image_sample_2d_v4f32(
-; GFX9-NEXT: main_body:
-; GFX9-NEXT: [[TEX:%.*]] = call <4 x half> @llvm.amdgcn.image.sample.lz.2d.v4f16.f32.v8i32.v4i32(i32 15, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
-; GFX9-NEXT: [[TEX_HALF_0:%.*]] = extractelement <4 x half> [[TEX]], i64 0
-; GFX9-NEXT: [[TEX_HALF_1:%.*]] = extractelement <4 x half> [[TEX]], i64 1
-; GFX9-NEXT: [[TEX_HALF_2:%.*]] = extractelement <4 x half> [[TEX]], i64 2
-; GFX9-NEXT: [[TEX_HALF_3:%.*]] = extractelement <4 x half> [[TEX]], i64 3
-; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
-; GFX9-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[TEX_HALF_2]], [[TEX_HALF_3]]
-; GFX9-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
-; GFX9-NEXT: ret half [[ADDF_SUM_2]]
-;
-; GFX10PLUS-LABEL: @image_sample_2d_v4f32(
-; GFX10PLUS-NEXT: main_body:
-; GFX10PLUS-NEXT: [[TEX:%.*]] = call <4 x half> @llvm.amdgcn.image.sample.lz.2d.v4f16.f32.v8i32.v4i32(i32 15, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
-; GFX10PLUS-NEXT: [[TEX_HALF_0:%.*]] = extractelement <4 x half> [[TEX]], i64 0
-; GFX10PLUS-NEXT: [[TEX_HALF_1:%.*]] = extractelement <4 x half> [[TEX]], i64 1
-; GFX10PLUS-NEXT: [[TEX_HALF_2:%.*]] = extractelement <4 x half> [[TEX]], i64 2
-; GFX10PLUS-NEXT: [[TEX_HALF_3:%.*]] = extractelement <4 x half> [[TEX]], i64 3
-; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
-; GFX10PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[TEX_HALF_2]], [[TEX_HALF_3]]
-; GFX10PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
-; GFX10PLUS-NEXT: ret half [[ADDF_SUM_2]]
-;
-; GFX11-LABEL: @image_sample_2d_v4f32(
-; GFX11-NEXT: main_body:
-; GFX11-NEXT: [[TEX:%.*]] = call <4 x half> @llvm.amdgcn.image.sample.lz.2d.v4f16.f32.v8i32.v4i32(i32 15, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
-; GFX11-NEXT: [[TEX_HALF_0:%.*]] = extractelement <4 x half> [[TEX]], i64 0
-; GFX11-NEXT: [[TEX_HALF_1:%.*]] = extractelement <4 x half> [[TEX]], i64 1
-; GFX11-NEXT: [[TEX_HALF_2:%.*]] = extractelement <4 x half> [[TEX]], i64 2
-; GFX11-NEXT: [[TEX_HALF_3:%.*]] = extractelement <4 x half> [[TEX]], i64 3
-; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
-; GFX11-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[TEX_HALF_2]], [[TEX_HALF_3]]
-; GFX11-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
-; GFX11-NEXT: ret half [[ADDF_SUM_2]]
-;
main_body:
%tex = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
%tex_4_half = fptrunc <4 x float> %tex to <4 x half>
@@ -230,7 +125,7 @@ main_body:
define void @image_sample_2d_multi_fptrunc_to_d16(<8 x i32> %surf_desc, <4 x i32> %samp, float %u, float %v, ptr addrspace(7) %out) {
; GFX7-LABEL: @image_sample_2d_multi_fptrunc_to_d16(
; GFX7-NEXT: main_body:
-; GFX7-NEXT: [[SAMPLE:%.*]] = call <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)
+; GFX7-NEXT: [[SAMPLE:%.*]] = call <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
; GFX7-NEXT: [[E0:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 0
; GFX7-NEXT: [[H0:%.*]] = fptrunc float [[E0]] to half
; GFX7-NEXT: [[E1:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 1
@@ -244,7 +139,7 @@ define void @image_sample_2d_multi_fptrunc_to_d16(<8 x i32> %surf_desc, <4 x i32
;
; GFX81PLUS-LABEL: @image_sample_2d_multi_fptrunc_to_d16(
; GFX81PLUS-NEXT: main_body:
-; GFX81PLUS-NEXT: [[SAMPLE:%.*]] = call <3 x half> @llvm.amdgcn.image.sample.lz.2d.v3f16.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)
+; GFX81PLUS-NEXT: [[SAMPLE:%.*]] = call <3 x half> @llvm.amdgcn.image.sample.lz.2d.v3f16.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
; GFX81PLUS-NEXT: [[H0:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 0
; GFX81PLUS-NEXT: [[H1:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 1
; GFX81PLUS-NEXT: [[H2:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 2
@@ -253,39 +148,6 @@ define void @image_sample_2d_multi_fptrunc_to_d16(<8 x i32> %surf_desc, <4 x i32
; GFX81PLUS-NEXT: store half [[RES]], ptr addrspace(7) [[OUT:%.*]], align 2
; GFX81PLUS-NEXT: ret void
;
-; GFX9-LABEL: @image_sample_2d_multi_fptrunc_to_d16(
-; GFX9-NEXT: main_body:
-; GFX9-NEXT: [[SAMPLE:%.*]] = call <3 x half> @llvm.amdgcn.image.sample.lz.2d.v3f16.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)
-; GFX9-NEXT: [[HALF_EXT2:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 0
-; GFX9-NEXT: [[HALF_EXT1:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 1
-; GFX9-NEXT: [[HALF_EXT:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 2
-; GFX9-NEXT: [[MUL:%.*]] = fmul half [[HALF_EXT2]], [[HALF_EXT1]]
-; GFX9-NEXT: [[RES:%.*]] = fadd half [[MUL]], [[HALF_EXT]]
-; GFX9-NEXT: store half [[RES]], ptr addrspace(7) [[OUT:%.*]], align 2
-; GFX9-NEXT: ret void
-;
-; GFX10PLUS-LABEL: @image_sample_2d_multi_fptrunc_to_d16(
-; GFX10PLUS-NEXT: main_body:
-; GFX10PLUS-NEXT: [[SAMPLE:%.*]] = call <3 x half> @llvm.amdgcn.image.sample.lz.2d.v3f16.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)
-; GFX10PLUS-NEXT: [[HALF_EXT2:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 0
-; GFX10PLUS-NEXT: [[HALF_EXT1:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 1
-; GFX10PLUS-NEXT: [[HALF_EXT:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 2
-; GFX10PLUS-NEXT: [[MUL:%.*]] = fmul half [[HALF_EXT2]], [[HALF_EXT1]]
-; GFX10PLUS-NEXT: [[RES:%.*]] = fadd half [[MUL]], [[HALF_EXT]]
-; GFX10PLUS-NEXT: store half [[RES]], ptr addrspace(7) [[OUT:%.*]], align 2
-; GFX10PLUS-NEXT: ret void
-;
-; GFX11-LABEL: @image_sample_2d_multi_fptrunc_to_d16(
-; GFX11-NEXT: main_body:
-; GFX11-NEXT: [[SAMPLE:%.*]] = call <3 x half> @llvm.amdgcn.image.sample.lz.2d.v3f16.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)
-; GFX11-NEXT: [[HALF_EXT2:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 0
-; GFX11-NEXT: [[HALF_EXT1:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 1
-; GFX11-NEXT: [[HALF_EXT:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 2
-; GFX11-NEXT: [[MUL:%.*]] = fmul half [[HALF_EXT2]], [[HALF_EXT1]]
-; GFX11-NEXT: [[RES:%.*]] = fadd half [[MUL]], [[HALF_EXT]]
-; GFX11-NEXT: store half [[RES]], ptr addrspace(7) [[OUT:%.*]], align 2
-; GFX11-NEXT: ret void
-;
main_body:
%sample = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float %u, float %v, <8 x i32> %surf_desc, <4 x i32> %samp, i1 false, i32 0, i32 0)
%e0 = extractelement <4 x float> %sample, i32 0
@@ -326,42 +188,6 @@ define amdgpu_ps half @image_gather4_2d_v4f32(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX81PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_2]]
;
-; GFX9-LABEL: @image_gather4_2d_v4f32(
-; GFX9-NEXT: main_body:
-; GFX9-NEXT: [[TEX:%.*]] = call <4 x half> @llvm.amdgcn.image.gather4.2d.v4f16.f16.v8i32.v4i32(i32 1, half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
-; GFX9-NEXT: [[TEX_HALF_0:%.*]] = extractelement <4 x half> [[TEX]], i64 0
-; GFX9-NEXT: [[TEX_HALF_1:%.*]] = extractelement <4 x half> [[TEX]], i64 1
-; GFX9-NEXT: [[TEX_HALF_2:%.*]] = extractelement <4 x half> [[TEX]], i64 2
-; GFX9-NEXT: [[TEX_HALF_3:%.*]] = extractelement <4 x half> [[TEX]], i64 3
-; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
-; GFX9-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[TEX_HALF_2]], [[TEX_HALF_3]]
-; GFX9-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
-; GFX9-NEXT: ret half [[ADDF_SUM_2]]
-;
-; GFX10PLUS-LABEL: @image_gather4_2d_v4f32(
-; GFX10PLUS-NEXT: main_body:
-; GFX10PLUS-NEXT: [[TEX:%.*]] = call <4 x half> @llvm.amdgcn.image.gather4.2d.v4f16.f16.v8i32.v4i32(i32 1, half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
-; GFX10PLUS-NEXT: [[TEX_HALF_0:%.*]] = extractelement <4 x half> [[TEX]], i64 0
-; GFX10PLUS-NEXT: [[TEX_HALF_1:%.*]] = extractelement <4 x half> [[TEX]], i64 1
-; GFX10PLUS-NEXT: [[TEX_HALF_2:%.*]] = extractelement <4 x half> [[TEX]], i64 2
-; GFX10PLUS-NEXT: [[TEX_HALF_3:%.*]] = extractelement <4 x half> [[TEX]], i64 3
-; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
-; GFX10PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[TEX_HALF_2]], [[TEX_HALF_3]]
-; GFX10PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
-; GFX10PLUS-NEXT: ret half [[ADDF_SUM_2]]
-;
-; GFX11-LABEL: @image_gather4_2d_v4f32(
-; GFX11-NEXT: main_body:
-; GFX11-NEXT: [[TEX:%.*]] = call <4 x half> @llvm.amdgcn.image.gather4.2d.v4f16.f16.v8i32.v4i32(i32 1, half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
-; GFX11-NEXT: [[TEX_HALF_0:%.*]] = extractelement <4 x half> [[TEX]], i64 0
-; GFX11-NEXT: [[TEX_HALF_1:%.*]] = extractelement <4 x half> [[TEX]], i64 1
-; GFX11-NEXT: [[TEX_HALF_2:%.*]] = extractelement <4 x half> [[TEX]], i64 2
-; GFX11-NEXT: [[TEX_HALF_3:%.*]] = extractelement <4 x half> [[TEX]], i64 3
-; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]
-; GFX11-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[TEX_HALF_2]], [[TEX_HALF_3]]
-; GFX11-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
-; GFX11-NEXT: ret half [[ADDF_SUM_2]]
-;
main_body:
%tex = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f16.v8i32.v4i32(i32 1, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
%tex_4_half = fptrunc <4 x float> %tex to <4 x half>
@@ -384,18 +210,6 @@ define amdgpu_ps half @load_1d(i16 %s, <8 x i32> inreg %rsrc) {
; GFX81PLUS-LABEL: @load_1d(
; GFX81PLUS-NEXT: [[S_FLOAT:%.*]] = call half @llvm.amdgcn.image.load.1d.f16.i16.v8i32(i32 1, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
; GFX81PLUS-NEXT: ret half [[S_FLOAT]]
-;
-; GFX9-LABEL: @load_1d(
-; GFX9-NEXT: [[S_FLOAT:%.*]] = call half @llvm.amdgcn.image.load.1d.f16.i16.v8i32(i32 1, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX9-NEXT: ret half [[S_FLOAT]]
-;
-; GFX10PLUS-LABEL: @load_1d(
-; GFX10PLUS-NEXT: [[S_FLOAT:%.*]] = call half @llvm.amdgcn.image.load.1d.f16.i16.v8i32(i32 1, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX10PLUS-NEXT: ret half [[S_FLOAT]]
-;
-; GFX11-LABEL: @load_1d(
-; GFX11-NEXT: [[S_FLOAT:%.*]] = call half @llvm.amdgcn.image.load.1d.f16.i16.v8i32(i32 1, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX11-NEXT: ret half [[S_FLOAT]]
;
%s_float = call float @llvm.amdgcn.image.load.1d.f32.i16.v8i32(i32 1, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
%s_half = fptrunc float %s_float to half
@@ -417,27 +231,6 @@ define amdgpu_ps half @load_1d_v2(i16 %s, <8 x i32> inreg %rsrc) {
; GFX81PLUS-NEXT: [[S1:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 1
; GFX81PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_0]]
-;
-; GFX9-LABEL: @load_1d_v2(
-; GFX9-NEXT: [[V2_FLOAT:%.*]] = call <2 x half> @llvm.amdgcn.image.load.1d.v2f16.i16.v8i32(i32 3, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX9-NEXT: [[S0:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 0
-; GFX9-NEXT: [[S1:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 1
-; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
-; GFX9-NEXT: ret half [[ADDF_SUM_0]]
-;
-; GFX10PLUS-LABEL: @load_1d_v2(
-; GFX10PLUS-NEXT: [[V2_FLOAT:%.*]] = call <2 x half> @llvm.amdgcn.image.load.1d.v2f16.i16.v8i32(i32 3, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX10PLUS-NEXT: [[S0:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 0
-; GFX10PLUS-NEXT: [[S1:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 1
-; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
-; GFX10PLUS-NEXT: ret half [[ADDF_SUM_0]]
-;
-; GFX11-LABEL: @load_1d_v2(
-; GFX11-NEXT: [[V2_FLOAT:%.*]] = call <2 x half> @llvm.amdgcn.image.load.1d.v2f16.i16.v8i32(i32 3, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX11-NEXT: [[S0:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 0
-; GFX11-NEXT: [[S1:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 1
-; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
-; GFX11-NEXT: ret half [[ADDF_SUM_0]]
;
%v2_float = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i16.v8i32(i32 3, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
%v2_half = fptrunc <2 x float> %v2_float to <2 x half>
@@ -466,33 +259,6 @@ define amdgpu_ps half @load_1d_v3(i16 %s, <8 x i32> inreg %rsrc) {
; GFX81PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
; GFX81PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_1]]
-;
-; GFX9-LABEL: @load_1d_v3(
-; GFX9-NEXT: [[V3_FLOAT:%.*]] = call <3 x half> @llvm.amdgcn.image.load.1d.v3f16.i16.v8i32(i32 7, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX9-NEXT: [[S0:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 0
-; GFX9-NEXT: [[S1:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 1
-; GFX9-NEXT: [[S2:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 2
-; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
-; GFX9-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]
-; GFX9-NEXT: ret half [[ADDF_SUM_1]]
-;
-; GFX10PLUS-LABEL: @load_1d_v3(
-; GFX10PLUS-NEXT: [[V3_FLOAT:%.*]] = call <3 x half> @llvm.amdgcn.image.load.1d.v3f16.i16.v8i32(i32 7, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX10PLUS-NEXT: [[S0:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 0
-; GFX10PLUS-NEXT: [[S1:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 1
-; GFX10PLUS-NEXT: [[S2:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 2
-; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
-; GFX10PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]
-; GFX10PLUS-NEXT: ret half [[ADDF_SUM_1]]
-;
-; GFX11-LABEL: @load_1d_v3(
-; GFX11-NEXT: [[V3_FLOAT:%.*]] = call <3 x half> @llvm.amdgcn.image.load.1d.v3f16.i16.v8i32(i32 7, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX11-NEXT: [[S0:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 0
-; GFX11-NEXT: [[S1:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 1
-; GFX11-NEXT: [[S2:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 2
-; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
-; GFX11-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]
-; GFX11-NEXT: ret half [[ADDF_SUM_1]]
;
%v3_float = call <3 x float> @llvm.amdgcn.image.load.1d.v3f32.i16.v8i32(i32 7, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
%v3_half = fptrunc <3 x float> %v3_float to <3 x half>
@@ -527,39 +293,6 @@ define amdgpu_ps half @load_1d_v4(i16 %s, <8 x i32> inreg %rsrc) {
; GFX81PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[S3]]
; GFX81PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_2]]
-;
-; GFX9-LABEL: @load_1d_v4(
-; GFX9-NEXT: [[V4_FLOAT:%.*]] = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16.v8i32(i32 15, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX9-NEXT: [[S0:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 0
-; GFX9-NEXT: [[S1:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 1
-; GFX9-NEXT: [[S2:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 2
-; GFX9-NEXT: [[S3:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 3
-; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
-; GFX9-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[S3]]
-; GFX9-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
-; GFX9-NEXT: ret half [[ADDF_SUM_2]]
-;
-; GFX10PLUS-LABEL: @load_1d_v4(
-; GFX10PLUS-NEXT: [[V4_FLOAT:%.*]] = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16.v8i32(i32 15, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX10PLUS-NEXT: [[S0:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 0
-; GFX10PLUS-NEXT: [[S1:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 1
-; GFX10PLUS-NEXT: [[S2:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 2
-; GFX10PLUS-NEXT: [[S3:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 3
-; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
-; GFX10PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[S3]]
-; GFX10PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
-; GFX10PLUS-NEXT: ret half [[ADDF_SUM_2]]
-;
-; GFX11-LABEL: @load_1d_v4(
-; GFX11-NEXT: [[V4_FLOAT:%.*]] = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16.v8i32(i32 15, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX11-NEXT: [[S0:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 0
-; GFX11-NEXT: [[S1:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 1
-; GFX11-NEXT: [[S2:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 2
-; GFX11-NEXT: [[S3:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 3
-; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
-; GFX11-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[S3]]
-; GFX11-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
-; GFX11-NEXT: ret half [[ADDF_SUM_2]]
;
%v4_float = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16.v8i32(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
%v4_half = fptrunc <4 x float> %v4_float to <4 x half>
@@ -585,21 +318,6 @@ define amdgpu_ps half @load_2dmsaa(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %f
; GFX81PLUS-NEXT: [[S_FLOAT:%.*]] = call half @llvm.amdgcn.image.msaa.load.x.2dmsaa.f16.i32.v8i32(i32 1, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
; GFX81PLUS-NEXT: ret half [[S_FLOAT]]
;
-; GFX9-LABEL: @load_2dmsaa(
-; GFX9-NEXT: main_body:
-; GFX9-NEXT: [[S_FLOAT:%.*]] = call half @llvm.amdgcn.image.msaa.load.x.2dmsaa.f16.i32.v8i32(i32 1, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX9-NEXT: ret half [[S_FLOAT]]
-;
-; GFX10PLUS-LABEL: @load_2dmsaa(
-; GFX10PLUS-NEXT: main_body:
-; GFX10PLUS-NEXT: [[S_FLOAT:%.*]] = call half @llvm.amdgcn.image.msaa.load.x.2dmsaa.f16.i32.v8i32(i32 1, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX10PLUS-NEXT: ret half [[S_FLOAT]]
-;
-; GFX11-LABEL: @load_2dmsaa(
-; GFX11-NEXT: main_body:
-; GFX11-NEXT: [[S_FLOAT:%.*]] = call half @llvm.amdgcn.image.msaa.load.x.2dmsaa.f16.i32.v8i32(i32 1, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX11-NEXT: ret half [[S_FLOAT]]
-;
main_body:
%s_float = call float @llvm.amdgcn.image.msaa.load.x.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
%s_half = fptrunc float %s_float to half
@@ -624,30 +342,6 @@ define amdgpu_ps half @load_2dmsaa_v2(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32
; GFX81PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_0]]
;
-; GFX9-LABEL: @load_2dmsaa_v2(
-; GFX9-NEXT: main_body:
-; GFX9-NEXT: [[V2_FLOAT:%.*]] = call <2 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v2f16.i32.v8i32(i32 3, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX9-NEXT: [[S0:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 0
-; GFX9-NEXT: [[S1:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 1
-; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
-; GFX9-NEXT: ret half [[ADDF_SUM_0]]
-;
-; GFX10PLUS-LABEL: @load_2dmsaa_v2(
-; GFX10PLUS-NEXT: main_body:
-; GFX10PLUS-NEXT: [[V2_FLOAT:%.*]] = call <2 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v2f16.i32.v8i32(i32 3, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX10PLUS-NEXT: [[S0:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 0
-; GFX10PLUS-NEXT: [[S1:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 1
-; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
-; GFX10PLUS-NEXT: ret half [[ADDF_SUM_0]]
-;
-; GFX11-LABEL: @load_2dmsaa_v2(
-; GFX11-NEXT: main_body:
-; GFX11-NEXT: [[V2_FLOAT:%.*]] = call <2 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v2f16.i32.v8i32(i32 3, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX11-NEXT: [[S0:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 0
-; GFX11-NEXT: [[S1:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 1
-; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
-; GFX11-NEXT: ret half [[ADDF_SUM_0]]
-;
main_body:
%v2_float = call <2 x float> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v2f32.i32.v8i32(i32 3, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
%v2_half = fptrunc <2 x float> %v2_float to <2 x half>
@@ -679,36 +373,6 @@ define amdgpu_ps half @load_2dmsaa_v3(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32
; GFX81PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_1]]
;
-; GFX9-LABEL: @load_2dmsaa_v3(
-; GFX9-NEXT: main_body:
-; GFX9-NEXT: [[V3_FLOAT:%.*]] = call <3 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v3f16.i32.v8i32(i32 7, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX9-NEXT: [[S0:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 0
-; GFX9-NEXT: [[S1:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 1
-; GFX9-NEXT: [[S2:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 2
-; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
-; GFX9-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]
-; GFX9-NEXT: ret half [[ADDF_SUM_1]]
-;
-; GFX10PLUS-LABEL: @load_2dmsaa_v3(
-; GFX10PLUS-NEXT: main_body:
-; GFX10PLUS-NEXT: [[V3_FLOAT:%.*]] = call <3 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v3f16.i32.v8i32(i32 7, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX10PLUS-NEXT: [[S0:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 0
-; GFX10PLUS-NEXT: [[S1:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 1
-; GFX10PLUS-NEXT: [[S2:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 2
-; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
-; GFX10PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]
-; GFX10PLUS-NEXT: ret half [[ADDF_SUM_1]]
-;
-; GFX11-LABEL: @load_2dmsaa_v3(
-; GFX11-NEXT: main_body:
-; GFX11-NEXT: [[V3_FLOAT:%.*]] = call <3 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v3f16.i32.v8i32(i32 7, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX11-NEXT: [[S0:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 0
-; GFX11-NEXT: [[S1:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 1
-; GFX11-NEXT: [[S2:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 2
-; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
-; GFX11-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]
-; GFX11-NEXT: ret half [[ADDF_SUM_1]]
-;
main_body:
%v3_float = call <3 x float> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v3f32.i32.v8i32(i32 7, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
%v3_half = fptrunc <3 x float> %v3_float to <3 x half>
@@ -746,42 +410,6 @@ define amdgpu_ps half @load_2dmsaa_v4(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32
; GFX81PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
; GFX81PLUS-NEXT: ret half [[ADDF_SUM_2]]
;
-; GFX9-LABEL: @load_2dmsaa_v4(
-; GFX9-NEXT: main_body:
-; GFX9-NEXT: [[V4_FLOAT:%.*]] = call <4 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v4f16.i32.v8i32(i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX9-NEXT: [[S0:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 0
-; GFX9-NEXT: [[S1:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 1
-; GFX9-NEXT: [[S2:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 2
-; GFX9-NEXT: [[S3:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 3
-; GFX9-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
-; GFX9-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[S3]]
-; GFX9-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
-; GFX9-NEXT: ret half [[ADDF_SUM_2]]
-;
-; GFX10PLUS-LABEL: @load_2dmsaa_v4(
-; GFX10PLUS-NEXT: main_body:
-; GFX10PLUS-NEXT: [[V4_FLOAT:%.*]] = call <4 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v4f16.i32.v8i32(i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX10PLUS-NEXT: [[S0:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 0
-; GFX10PLUS-NEXT: [[S1:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 1
-; GFX10PLUS-NEXT: [[S2:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 2
-; GFX10PLUS-NEXT: [[S3:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 3
-; GFX10PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
-; GFX10PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[S3]]
-; GFX10PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
-; GFX10PLUS-NEXT: ret half [[ADDF_SUM_2]]
-;
-; GFX11-LABEL: @load_2dmsaa_v4(
-; GFX11-NEXT: main_body:
-; GFX11-NEXT: [[V4_FLOAT:%.*]] = call <4 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v4f16.i32.v8i32(i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
-; GFX11-NEXT: [[S0:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 0
-; GFX11-NEXT: [[S1:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 1
-; GFX11-NEXT: [[S2:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 2
-; GFX11-NEXT: [[S3:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 3
-; GFX11-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]
-; GFX11-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[S3]]
-; GFX11-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]
-; GFX11-NEXT: ret half [[ADDF_SUM_2]]
-;
main_body:
%v4_float = call <4 x float> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v4f32.i32.v8i32(i32 15, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
%v4_half = fptrunc <4 x float> %v4_float to <4 x half>
>From 059a43697a1188cc143db5a52bd5ee6f12929090 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Thu, 29 May 2025 12:48:06 +0800
Subject: [PATCH 3/6] [AMDGPU] Add two negative tests.
---
.../InstCombine/AMDGPU/image-d16.ll | 91 +++++++++++++++++--
1 file changed, 84 insertions(+), 7 deletions(-)
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll b/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll
index 27876b7dbc1e6..720f0c1b28b42 100644
--- a/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll
@@ -122,7 +122,7 @@ main_body:
ret half %addf_sum.2
}
-define void @image_sample_2d_multi_fptrunc_to_d16(<8 x i32> %surf_desc, <4 x i32> %samp, float %u, float %v, ptr addrspace(7) %out) {
+define amdgpu_gs half @image_sample_2d_multi_fptrunc_to_d16(<8 x i32> %surf_desc, <4 x i32> %samp, float %u, float %v) {
; GFX7-LABEL: @image_sample_2d_multi_fptrunc_to_d16(
; GFX7-NEXT: main_body:
; GFX7-NEXT: [[SAMPLE:%.*]] = call <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
@@ -134,8 +134,7 @@ define void @image_sample_2d_multi_fptrunc_to_d16(<8 x i32> %surf_desc, <4 x i32
; GFX7-NEXT: [[H2:%.*]] = fptrunc float [[E2]] to half
; GFX7-NEXT: [[MUL:%.*]] = fmul half [[H0]], [[H1]]
; GFX7-NEXT: [[RES:%.*]] = fadd half [[MUL]], [[H2]]
-; GFX7-NEXT: store half [[RES]], ptr addrspace(7) [[OUT:%.*]], align 2
-; GFX7-NEXT: ret void
+; GFX7-NEXT: ret half [[RES]]
;
; GFX81PLUS-LABEL: @image_sample_2d_multi_fptrunc_to_d16(
; GFX81PLUS-NEXT: main_body:
@@ -145,8 +144,7 @@ define void @image_sample_2d_multi_fptrunc_to_d16(<8 x i32> %surf_desc, <4 x i32
; GFX81PLUS-NEXT: [[H2:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 2
; GFX81PLUS-NEXT: [[MUL:%.*]] = fmul half [[H0]], [[H1]]
; GFX81PLUS-NEXT: [[RES:%.*]] = fadd half [[MUL]], [[H2]]
-; GFX81PLUS-NEXT: store half [[RES]], ptr addrspace(7) [[OUT:%.*]], align 2
-; GFX81PLUS-NEXT: ret void
+; GFX81PLUS-NEXT: ret half [[RES]]
;
main_body:
%sample = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float %u, float %v, <8 x i32> %surf_desc, <4 x i32> %samp, i1 false, i32 0, i32 0)
@@ -158,8 +156,87 @@ main_body:
%h2 = fptrunc float %e2 to half
%mul = fmul half %h0, %h1
%res = fadd half %mul, %h2
- store half %res, ptr addrspace(7) %out, align 2
- ret void
+ ret half %res
+}
+
+define amdgpu_gs half @image_sample_2d_extractelement_multi_use_no_d16(<8 x i32> %surf_desc, <4 x i32> %sampler_desc, float %u, float %v) {
+; GFX7-LABEL: @image_sample_2d_extractelement_multi_use_no_d16(
+; GFX7-NEXT: main_body:
+; GFX7-NEXT: [[SAMPLE:%.*]] = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32.v8i32.v4i32(i32 3, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)
+; GFX7-NEXT: [[E0:%.*]] = extractelement <2 x float> [[SAMPLE]], i64 0
+; GFX7-NEXT: [[H0:%.*]] = fptrunc float [[E0]] to half
+; GFX7-NEXT: [[USER2:%.*]] = fadd float [[E0]], 1.000000e+00
+; GFX7-NEXT: [[HALF:%.*]] = fptrunc float [[USER2]] to half
+; GFX7-NEXT: [[E1:%.*]] = extractelement <2 x float> [[SAMPLE]], i64 1
+; GFX7-NEXT: [[H1:%.*]] = fptrunc float [[E1]] to half
+; GFX7-NEXT: [[MUL:%.*]] = fmul half [[H0]], [[H1]]
+; GFX7-NEXT: [[RES:%.*]] = fadd half [[MUL]], [[HALF]]
+; GFX7-NEXT: ret half [[RES]]
+;
+; GFX81PLUS-LABEL: @image_sample_2d_extractelement_multi_use_no_d16(
+; GFX81PLUS-NEXT: main_body:
+; GFX81PLUS-NEXT: [[SAMPLE:%.*]] = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32.v8i32.v4i32(i32 3, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)
+; GFX81PLUS-NEXT: [[E0:%.*]] = extractelement <2 x float> [[SAMPLE]], i64 0
+; GFX81PLUS-NEXT: [[H0:%.*]] = fptrunc float [[E0]] to half
+; GFX81PLUS-NEXT: [[USER2:%.*]] = fadd float [[E0]], 1.000000e+00
+; GFX81PLUS-NEXT: [[HALF:%.*]] = fptrunc float [[USER2]] to half
+; GFX81PLUS-NEXT: [[E1:%.*]] = extractelement <2 x float> [[SAMPLE]], i64 1
+; GFX81PLUS-NEXT: [[H1:%.*]] = fptrunc float [[E1]] to half
+; GFX81PLUS-NEXT: [[MUL:%.*]] = fmul half [[H0]], [[H1]]
+; GFX81PLUS-NEXT: [[RES:%.*]] = fadd half [[MUL]], [[HALF]]
+; GFX81PLUS-NEXT: ret half [[RES]]
+;
+main_body:
+ %sample = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float %u, float %v, <8 x i32> %surf_desc, <4 x i32> %sampler_desc, i1 false, i32 0, i32 0)
+ %e0 = extractelement <4 x float> %sample, i32 0
+ %h0 = fptrunc float %e0 to half
+ %user2 = fadd float %e0, 1.0
+ %half = fptrunc float %user2 to half
+ %e1 = extractelement <4 x float> %sample, i32 1
+ %h1 = fptrunc float %e1 to half
+ %mul = fmul half %h0, %h1
+ %res = fadd half %mul, %half
+ ret half %res
+}
+
+define amdgpu_gs bfloat @image_sample_2d_multi_fptrunc_non_half_no_d16(<8 x i32> %surf_desc, <4 x i32> %sampler_desc, float %u, float %v) {
+; GFX7-LABEL: @image_sample_2d_multi_fptrunc_non_half_no_d16(
+; GFX7-NEXT: main_body:
+; GFX7-NEXT: [[SAMPLE:%.*]] = call <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)
+; GFX7-NEXT: [[E0:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 0
+; GFX7-NEXT: [[H0:%.*]] = fptrunc float [[E0]] to bfloat
+; GFX7-NEXT: [[E1:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 1
+; GFX7-NEXT: [[H1:%.*]] = fptrunc float [[E1]] to bfloat
+; GFX7-NEXT: [[E2:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 2
+; GFX7-NEXT: [[H2:%.*]] = fptrunc float [[E2]] to bfloat
+; GFX7-NEXT: [[MUL:%.*]] = fmul bfloat [[H0]], [[H1]]
+; GFX7-NEXT: [[RES:%.*]] = fadd bfloat [[MUL]], [[H2]]
+; GFX7-NEXT: ret bfloat [[RES]]
+;
+; GFX81PLUS-LABEL: @image_sample_2d_multi_fptrunc_non_half_no_d16(
+; GFX81PLUS-NEXT: main_body:
+; GFX81PLUS-NEXT: [[SAMPLE:%.*]] = call <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)
+; GFX81PLUS-NEXT: [[E0:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 0
+; GFX81PLUS-NEXT: [[H0:%.*]] = fptrunc float [[E0]] to bfloat
+; GFX81PLUS-NEXT: [[E1:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 1
+; GFX81PLUS-NEXT: [[H1:%.*]] = fptrunc float [[E1]] to bfloat
+; GFX81PLUS-NEXT: [[E2:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 2
+; GFX81PLUS-NEXT: [[H2:%.*]] = fptrunc float [[E2]] to bfloat
+; GFX81PLUS-NEXT: [[MUL:%.*]] = fmul bfloat [[H0]], [[H1]]
+; GFX81PLUS-NEXT: [[RES:%.*]] = fadd bfloat [[MUL]], [[H2]]
+; GFX81PLUS-NEXT: ret bfloat [[RES]]
+;
+main_body:
+ %sample = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float %u, float %v, <8 x i32> %surf_desc, <4 x i32> %sampler_desc, i1 false, i32 0, i32 0)
+ %e0 = extractelement <4 x float> %sample, i32 0
+ %h0 = fptrunc float %e0 to bfloat
+ %e1 = extractelement <4 x float> %sample, i32 1
+ %h1 = fptrunc float %e1 to bfloat
+ %e2 = extractelement <4 x float> %sample, i32 2
+ %h2 = fptrunc float %e2 to bfloat
+ %mul = fmul bfloat %h0, %h1
+ %res = fadd bfloat %mul, %h2
+ ret bfloat %res
}
define amdgpu_ps half @image_gather4_2d_v4f32(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {
>From 760277d73f04f3c344f807cda12d08a0d793e516 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Sun, 8 Jun 2025 08:09:42 +0000
Subject: [PATCH 4/6] [AMDGPU] Update lit test.
---
llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll b/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll
index 720f0c1b28b42..ee5ccf5af987d 100644
--- a/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/image-d16.ll
@@ -122,7 +122,7 @@ main_body:
ret half %addf_sum.2
}
-define amdgpu_gs half @image_sample_2d_multi_fptrunc_to_d16(<8 x i32> %surf_desc, <4 x i32> %samp, float %u, float %v) {
+define amdgpu_ps half @image_sample_2d_multi_fptrunc_to_d16(<8 x i32> %surf_desc, <4 x i32> %samp, float %u, float %v) {
; GFX7-LABEL: @image_sample_2d_multi_fptrunc_to_d16(
; GFX7-NEXT: main_body:
; GFX7-NEXT: [[SAMPLE:%.*]] = call <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
@@ -159,7 +159,7 @@ main_body:
ret half %res
}
-define amdgpu_gs half @image_sample_2d_extractelement_multi_use_no_d16(<8 x i32> %surf_desc, <4 x i32> %sampler_desc, float %u, float %v) {
+define amdgpu_ps half @image_sample_2d_extractelement_multi_use_no_d16(<8 x i32> %surf_desc, <4 x i32> %sampler_desc, float %u, float %v) {
; GFX7-LABEL: @image_sample_2d_extractelement_multi_use_no_d16(
; GFX7-NEXT: main_body:
; GFX7-NEXT: [[SAMPLE:%.*]] = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32.v8i32.v4i32(i32 3, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)
@@ -199,7 +199,7 @@ main_body:
ret half %res
}
-define amdgpu_gs bfloat @image_sample_2d_multi_fptrunc_non_half_no_d16(<8 x i32> %surf_desc, <4 x i32> %sampler_desc, float %u, float %v) {
+define amdgpu_ps bfloat @image_sample_2d_multi_fptrunc_non_half_no_d16(<8 x i32> %surf_desc, <4 x i32> %sampler_desc, float %u, float %v) {
; GFX7-LABEL: @image_sample_2d_multi_fptrunc_non_half_no_d16(
; GFX7-NEXT: main_body:
; GFX7-NEXT: [[SAMPLE:%.*]] = call <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)
>From 887688e622a130665dcc87eba984873e4dbec3fc Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Mon, 16 Jun 2025 14:02:29 +0800
Subject: [PATCH 5/6] [AMDGPU] Update for comments.
---
.../AMDGPU/AMDGPUInstCombineIntrinsic.cpp | 95 +++++++++----------
1 file changed, 46 insertions(+), 49 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
index 998f96870a667..555816467e882 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
@@ -269,66 +269,63 @@ simplifyAMDGCNImageIntrinsic(const GCNSubtarget *ST,
ArgTys[0] = User->getType();
});
}
- } else {
- // Only perform D16 folding if every user of the image sample is
- // an ExtractElementInst immediately followed by an FPTrunc to half.
- SmallVector<ExtractElementInst *, 4> Extracts;
- SmallVector<FPTruncInst *, 4> Truncs;
- bool AllHalfExtracts = true;
-
- for (User *U : II.users()) {
- auto *Ext = dyn_cast<ExtractElementInst>(U);
- if (!Ext || !Ext->hasOneUse()) {
- AllHalfExtracts = false;
- break;
- }
- auto *Tr = dyn_cast<FPTruncInst>(*Ext->user_begin());
- if (!Tr || !Tr->getType()->isHalfTy()) {
- AllHalfExtracts = false;
- break;
- }
- Extracts.push_back(Ext);
- Truncs.push_back(Tr);
- }
+ }
- if (AllHalfExtracts && !Extracts.empty()) {
- auto *VecTy = cast<VectorType>(II.getType());
- Type *HalfVecTy =
- VecTy->getWithNewType(Type::getHalfTy(II.getContext()));
+ // Only perform D16 folding if every user of the image sample is
+ // an ExtractElementInst immediately followed by an FPTrunc to half.
+ SmallVector<ExtractElementInst *, 4> Extracts;
+ SmallVector<FPTruncInst *, 4> Truncs;
- // Obtain the original image sample intrinsic's signature
- // and replace its return type with the half-vector for D16 folding
- SmallVector<Type *, 8> SigTys;
- Intrinsic::getIntrinsicSignature(II.getCalledFunction(), SigTys);
- SigTys[0] = HalfVecTy;
+ for (User *U : II.users()) {
+ auto *Ext = dyn_cast<ExtractElementInst>(U);
+ if (!Ext || !Ext->hasOneUse())
+ return std::nullopt;
- Module *M = II.getModule();
- Function *HalfDecl =
- Intrinsic::getOrInsertDeclaration(M, ImageDimIntr->Intr, SigTys);
+ auto *Tr = dyn_cast<FPTruncInst>(*Ext->user_begin());
+ if (!Tr || !Tr->getType()->isHalfTy())
+ return std::nullopt;
- II.mutateType(HalfVecTy);
- II.setCalledFunction(HalfDecl);
+ Extracts.push_back(Ext);
+ Truncs.push_back(Tr);
+ }
- IRBuilder<> Builder(II.getContext());
- for (auto [Ext, Tr] : zip(Extracts, Truncs)) {
- Value *Idx = Ext->getIndexOperand();
+ if (Extracts.empty())
+ return std::nullopt;
- Builder.SetInsertPoint(Tr);
+ auto *VecTy = cast<VectorType>(II.getType());
+ Type *HalfVecTy = VecTy->getWithNewType(Type::getHalfTy(II.getContext()));
- Value *HalfExtract = Builder.CreateExtractElement(&II, Idx);
- HalfExtract->takeName(Tr);
+ // Obtain the original image sample intrinsic's signature
+ // and replace its return type with the half-vector for D16 folding
+ SmallVector<Type *, 8> SigTys;
+ Intrinsic::getIntrinsicSignature(II.getCalledFunction(), SigTys);
+ SigTys[0] = HalfVecTy;
- Tr->replaceAllUsesWith(HalfExtract);
- }
+ Module *M = II.getModule();
+ Function *HalfDecl =
+ Intrinsic::getOrInsertDeclaration(M, ImageDimIntr->Intr, SigTys);
- for (FPTruncInst *T : Truncs)
- IC.eraseInstFromFunction(*T);
- for (ExtractElementInst *E : Extracts)
- IC.eraseInstFromFunction(*E);
+ II.mutateType(HalfVecTy);
+ II.setCalledFunction(HalfDecl);
- return &II;
- }
+ IRBuilder<> Builder(II.getContext());
+ for (auto [Ext, Tr] : zip(Extracts, Truncs)) {
+ Value *Idx = Ext->getIndexOperand();
+
+ Builder.SetInsertPoint(Tr);
+
+ Value *HalfExtract = Builder.CreateExtractElement(&II, Idx);
+ HalfExtract->takeName(Tr);
+
+ Tr->replaceAllUsesWith(HalfExtract);
}
+
+ for (FPTruncInst *T : Truncs)
+ IC.eraseInstFromFunction(*T);
+ for (ExtractElementInst *E : Extracts)
+ IC.eraseInstFromFunction(*E);
+
+ return &II;
}
}
>From d26b66ff720abd5c1fedb08e8fa9011dfadae654 Mon Sep 17 00:00:00 2001
From: Harrison Hao <tsworld1314 at gmail.com>
Date: Tue, 17 Jun 2025 14:25:53 +0800
Subject: [PATCH 6/6] [AMDGPU] use std pair.
---
.../AMDGPU/AMDGPUInstCombineIntrinsic.cpp | 19 +++++++++----------
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
index 555816467e882..ced0f265df7c4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
@@ -273,8 +273,8 @@ simplifyAMDGCNImageIntrinsic(const GCNSubtarget *ST,
// Only perform D16 folding if every user of the image sample is
// an ExtractElementInst immediately followed by an FPTrunc to half.
- SmallVector<ExtractElementInst *, 4> Extracts;
- SmallVector<FPTruncInst *, 4> Truncs;
+ SmallVector<std::pair<ExtractElementInst *, FPTruncInst *>, 4>
+ ExtractTruncPairs;
for (User *U : II.users()) {
auto *Ext = dyn_cast<ExtractElementInst>(U);
@@ -285,11 +285,10 @@ simplifyAMDGCNImageIntrinsic(const GCNSubtarget *ST,
if (!Tr || !Tr->getType()->isHalfTy())
return std::nullopt;
- Extracts.push_back(Ext);
- Truncs.push_back(Tr);
+ ExtractTruncPairs.emplace_back(Ext, Tr);
}
- if (Extracts.empty())
+ if (ExtractTruncPairs.empty())
return std::nullopt;
auto *VecTy = cast<VectorType>(II.getType());
@@ -309,7 +308,7 @@ simplifyAMDGCNImageIntrinsic(const GCNSubtarget *ST,
II.setCalledFunction(HalfDecl);
IRBuilder<> Builder(II.getContext());
- for (auto [Ext, Tr] : zip(Extracts, Truncs)) {
+ for (auto &[Ext, Tr] : ExtractTruncPairs) {
Value *Idx = Ext->getIndexOperand();
Builder.SetInsertPoint(Tr);
@@ -320,10 +319,10 @@ simplifyAMDGCNImageIntrinsic(const GCNSubtarget *ST,
Tr->replaceAllUsesWith(HalfExtract);
}
- for (FPTruncInst *T : Truncs)
- IC.eraseInstFromFunction(*T);
- for (ExtractElementInst *E : Extracts)
- IC.eraseInstFromFunction(*E);
+ for (auto &[Ext, Tr] : ExtractTruncPairs) {
+ IC.eraseInstFromFunction(*Tr);
+ IC.eraseInstFromFunction(*Ext);
+ }
return &II;
}
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