[llvm] [AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (PR #140694)

[Chris Jackson via llvm-commits]

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@@ -4056,6 +4058,51 @@ SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
   SDLoc SL(N);
   SelectionDAG &DAG = DCI.DAG;
 
+    // When the shl64_reduce optimisation code is passed through vector
+  // legalization
+  // some scalarising occurs. After ISD::AND was legalised, this resulted in the
+  // AND instructions no longer being elided, as mentioned below. The following
+  // code should make sure this takes please.
+  if (RHS->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+    SDValue VAND = RHS.getOperand(0);
+    uint64_t AndIndex = RHS->getConstantOperandVal(1);
+    if (VAND->getOpcode() == ISD::AND) {
+      SDValue LHSAND = VAND.getOperand(0);
+      SDValue RHSAND = VAND.getOperand(1);
+      if (RHSAND->getOpcode() == ISD::BUILD_VECTOR)
+          if (RHSAND->getConstantOperandVal(0) == 0x1f &&
+              RHSAND->getConstantOperandVal(1) == 0x1f) {
+            // Get the non-const AND operands and produce scalar AND
+            const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
+            const SDValue One = DAG.getConstant(1, SL, MVT::i32);
+            SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, LHSAND, Zero);
+            SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, LHSAND, One);
+            SDValue AndMask = DAG.getConstant(0x1f, SL, MVT::i32);
+            SDValue LoAnd = DAG.getNode(ISD::AND, SL, MVT::i32, Lo, AndMask);
+            SDValue HiAnd = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, AndMask);
+
+            if(AndIndex == 0) {
+                SDValue TLo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
+                return DAG.getNode(ISD::SHL, SL, MVT::i32, TLo, LoAnd, N->getFlags());
+            } 
+            else if (AndIndex == 1) {
+              SDValue TLo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
+              return DAG.getNode(ISD::SHL, SL, MVT::i32, TLo, HiAnd, N->getFlags());
+            }
+
+            // // Now produce the scalar SHL operations.
+            
+            // SDValue truncShiftAmt = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, RHS);
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chrisjbris wrote:

Yes, removed, thanks.

https://github.com/llvm/llvm-project/pull/140694