[llvm] [AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (PR #140694)

[Shilei Tian via llvm-commits]

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@@ -4056,6 +4058,51 @@ SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
   SDLoc SL(N);
   SelectionDAG &DAG = DCI.DAG;
 
+    // When the shl64_reduce optimisation code is passed through vector
+  // legalization
+  // some scalarising occurs. After ISD::AND was legalised, this resulted in the
+  // AND instructions no longer being elided, as mentioned below. The following
+  // code should make sure this takes please.
+  if (RHS->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+    SDValue VAND = RHS.getOperand(0);
+    uint64_t AndIndex = RHS->getConstantOperandVal(1);
+    if (VAND->getOpcode() == ISD::AND) {
+      SDValue LHSAND = VAND.getOperand(0);
+      SDValue RHSAND = VAND.getOperand(1);
+      if (RHSAND->getOpcode() == ISD::BUILD_VECTOR)
+          if (RHSAND->getConstantOperandVal(0) == 0x1f &&
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shiltian wrote:

can you briefly describe the intention of this check, esp. things like the rationale behind `0x1f`

https://github.com/llvm/llvm-project/pull/140694