[llvm] [AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (PR #140694)

[Shilei Tian via llvm-commits]

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@@ -4056,6 +4058,51 @@ SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
   SDLoc SL(N);
   SelectionDAG &DAG = DCI.DAG;
 
+    // When the shl64_reduce optimisation code is passed through vector
+  // legalization
+  // some scalarising occurs. After ISD::AND was legalised, this resulted in the
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shiltian wrote:

line break is off

https://github.com/llvm/llvm-project/pull/140694