[llvm] [TableGen] Use default member initializers. NFC. (PR #144349)
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Mon Jun 16 06:16:45 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-selectiondag
@llvm/pr-subscribers-llvm-globalisel
Author: Jay Foad (jayfoad)
<details>
<summary>Changes</summary>
Automated with clang-tidy -fix -checks=-*,modernize-use-default-member-init
---
Full diff: https://github.com/llvm/llvm-project/pull/144349.diff
10 Files Affected:
- (modified) llvm/utils/TableGen/AsmMatcherEmitter.cpp (+4-5)
- (modified) llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp (+8-10)
- (modified) llvm/utils/TableGen/Common/CodeGenRegisters.cpp (+2-2)
- (modified) llvm/utils/TableGen/Common/CodeGenRegisters.h (+4-6)
- (modified) llvm/utils/TableGen/Common/CodeGenSchedule.h (+7-7)
- (modified) llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h (+8-10)
- (modified) llvm/utils/TableGen/Common/PredicateExpander.h (+4-5)
- (modified) llvm/utils/TableGen/DAGISelMatcherGen.cpp (+4-5)
- (modified) llvm/utils/TableGen/DecoderEmitter.cpp (+2-3)
- (modified) llvm/utils/TableGen/FastISelEmitter.cpp (+2-2)
``````````diff
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 32098e96ce721..b6d9c9f3a1584 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -388,7 +388,7 @@ struct MatchableInfo {
StringRef Token;
/// The unique class instance this operand should match.
- ClassInfo *Class;
+ ClassInfo *Class = nullptr;
/// The operand name this is, if anything.
StringRef SrcOpName;
@@ -397,18 +397,17 @@ struct MatchableInfo {
StringRef OrigSrcOpName;
/// The suboperand index within SrcOpName, or -1 for the entire operand.
- int SubOpIdx;
+ int SubOpIdx = -1;
/// Whether the token is "isolated", i.e., it is preceded and followed
/// by separators.
bool IsIsolatedToken;
/// Register record if this token is singleton register.
- const Record *SingletonReg;
+ const Record *SingletonReg = nullptr;
explicit AsmOperand(bool IsIsolatedToken, StringRef T)
- : Token(T), Class(nullptr), SubOpIdx(-1),
- IsIsolatedToken(IsIsolatedToken), SingletonReg(nullptr) {}
+ : Token(T), IsIsolatedToken(IsIsolatedToken) {}
};
/// ResOperand - This represents a single operand in the result instruction
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index 810b35e65b310..3a4ca1b451567 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -3604,16 +3604,14 @@ class InstAnalyzer {
const CodeGenDAGPatterns &CDP;
public:
- bool hasSideEffects;
- bool mayStore;
- bool mayLoad;
- bool isBitcast;
- bool isVariadic;
- bool hasChain;
-
- InstAnalyzer(const CodeGenDAGPatterns &cdp)
- : CDP(cdp), hasSideEffects(false), mayStore(false), mayLoad(false),
- isBitcast(false), isVariadic(false), hasChain(false) {}
+ bool hasSideEffects = false;
+ bool mayStore = false;
+ bool mayLoad = false;
+ bool isBitcast = false;
+ bool isVariadic = false;
+ bool hasChain = false;
+
+ InstAnalyzer(const CodeGenDAGPatterns &cdp) : CDP(cdp) {}
void Analyze(const PatternToMatch &Pat) {
const TreePatternNode &N = Pat.getSrcPattern();
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index f52c21e97f9c8..57a243158692b 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -164,8 +164,8 @@ CodeGenRegister::CodeGenRegister(const Record *R, unsigned Enum)
: TheDef(R), EnumValue(Enum),
CostPerUse(R->getValueAsListOfInts("CostPerUse")),
CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")),
- HasDisjunctSubRegs(false), Constant(R->getValueAsBit("isConstant")),
- SubRegsComplete(false), SuperRegsComplete(false), TopoSig(~0u) {
+ Constant(R->getValueAsBit("isConstant")), SubRegsComplete(false),
+ SuperRegsComplete(false), TopoSig(~0u) {
Artificial = R->getValueAsBit("isArtificial");
}
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h
index 3f4c157fab69a..bbcd44ce2cc5b 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h
@@ -564,7 +564,7 @@ struct RegUnit {
// Weight assigned to this RegUnit for estimating register pressure.
// This is useful when equalizing weights in register classes with mixed
// register topologies.
- unsigned Weight;
+ unsigned Weight = 0;
// Each native RegUnit corresponds to one or two root registers. The full
// set of registers containing this unit can be computed as the union of
@@ -573,14 +573,12 @@ struct RegUnit {
// Index into RegClassUnitSets where we can find the list of UnitSets that
// contain this unit.
- unsigned RegClassUnitSetsIdx;
+ unsigned RegClassUnitSetsIdx = 0;
// A register unit is artificial if at least one of its roots is
// artificial.
- bool Artificial;
+ bool Artificial = false;
- RegUnit() : Weight(0), RegClassUnitSetsIdx(0), Artificial(false) {
- Roots[0] = Roots[1] = nullptr;
- }
+ RegUnit() { Roots[0] = Roots[1] = nullptr; }
ArrayRef<const CodeGenRegister *> getRoots() const {
assert(!(Roots[1] && !Roots[0]) && "Invalid roots array");
diff --git a/llvm/utils/TableGen/Common/CodeGenSchedule.h b/llvm/utils/TableGen/Common/CodeGenSchedule.h
index 697a1ce8f75ac..1d5e953cf70c7 100644
--- a/llvm/utils/TableGen/Common/CodeGenSchedule.h
+++ b/llvm/utils/TableGen/Common/CodeGenSchedule.h
@@ -193,7 +193,7 @@ struct CodeGenRegisterFile {
unsigned MaxMovesEliminatedPerCycle;
bool AllowZeroMoveEliminationOnly;
- unsigned NumPhysRegs;
+ unsigned NumPhysRegs = 0;
std::vector<CodeGenRegisterCost> Costs;
CodeGenRegisterFile(StringRef name, const Record *def,
@@ -201,7 +201,7 @@ struct CodeGenRegisterFile {
bool AllowZeroMoveElimOnly = false)
: Name(name), RegisterFileDef(def),
MaxMovesEliminatedPerCycle(MaxMoveElimPerCy),
- AllowZeroMoveEliminationOnly(AllowZeroMoveElimOnly), NumPhysRegs(0) {}
+ AllowZeroMoveEliminationOnly(AllowZeroMoveElimOnly) {}
bool hasDefaultCosts() const { return Costs.empty(); }
};
@@ -261,16 +261,16 @@ struct CodeGenProcModel {
std::vector<CodeGenRegisterFile> RegisterFiles;
// Optional Retire Control Unit definition.
- const Record *RetireControlUnit;
+ const Record *RetireControlUnit = nullptr;
// Load/Store queue descriptors.
- const Record *LoadQueue;
- const Record *StoreQueue;
+ const Record *LoadQueue = nullptr;
+ const Record *StoreQueue = nullptr;
CodeGenProcModel(unsigned Idx, std::string Name, const Record *MDef,
const Record *IDef)
- : Index(Idx), ModelName(std::move(Name)), ModelDef(MDef), ItinsDef(IDef),
- RetireControlUnit(nullptr), LoadQueue(nullptr), StoreQueue(nullptr) {}
+ : Index(Idx), ModelName(std::move(Name)), ModelDef(MDef), ItinsDef(IDef) {
+ }
bool hasItineraries() const {
return !ItinsDef->getValueAsListOfDefs("IID").empty();
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
index 66472576eea8f..620f88db66109 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
@@ -501,13 +501,13 @@ class RuleMatcher : public Matcher {
/// ID for the next instruction variable defined with
/// implicitlyDefineInsnVar()
- unsigned NextInsnVarID;
+ unsigned NextInsnVarID = 0;
/// ID for the next output instruction allocated with allocateOutputInsnID()
- unsigned NextOutputInsnID;
+ unsigned NextOutputInsnID = 0;
/// ID for the next temporary register ID allocated with allocateTempRegID()
- unsigned NextTempRegID;
+ unsigned NextTempRegID = 0;
/// ID for the next recorded type. Starts at -1 and counts down.
TempTypeIdx NextTempTypeIdx = -1;
@@ -545,9 +545,7 @@ class RuleMatcher : public Matcher {
StringRef FlagName, GISelFlags FlagBit);
public:
- RuleMatcher(ArrayRef<SMLoc> SrcLoc)
- : NextInsnVarID(0), NextOutputInsnID(0), NextTempRegID(0), SrcLoc(SrcLoc),
- RuleID(NextRuleID++) {}
+ RuleMatcher(ArrayRef<SMLoc> SrcLoc) : SrcLoc(SrcLoc), RuleID(NextRuleID++) {}
RuleMatcher(RuleMatcher &&Other) = default;
RuleMatcher &operator=(RuleMatcher &&Other) = default;
@@ -2039,12 +2037,12 @@ class CopyConstantAsImmRenderer : public OperandRenderer {
unsigned NewInsnID;
/// The name of the operand.
const std::string SymbolicName;
- bool Signed;
+ bool Signed = true;
public:
CopyConstantAsImmRenderer(unsigned NewInsnID, StringRef SymbolicName)
: OperandRenderer(OR_CopyConstantAsImm), NewInsnID(NewInsnID),
- SymbolicName(SymbolicName), Signed(true) {}
+ SymbolicName(SymbolicName) {}
static bool classof(const OperandRenderer *R) {
return R->getKind() == OR_CopyConstantAsImm;
@@ -2359,7 +2357,7 @@ class BuildMIAction : public MatchAction {
private:
unsigned InsnID;
const CodeGenInstruction *I;
- InstructionMatcher *Matched;
+ InstructionMatcher *Matched = nullptr;
std::vector<std::unique_ptr<OperandRenderer>> OperandRenderers;
SmallPtrSet<const Record *, 4> DeadImplicitDefs;
@@ -2372,7 +2370,7 @@ class BuildMIAction : public MatchAction {
public:
BuildMIAction(unsigned InsnID, const CodeGenInstruction *I)
- : MatchAction(AK_BuildMI), InsnID(InsnID), I(I), Matched(nullptr) {}
+ : MatchAction(AK_BuildMI), InsnID(InsnID), I(I) {}
static bool classof(const MatchAction *A) {
return A->getKind() == AK_BuildMI;
diff --git a/llvm/utils/TableGen/Common/PredicateExpander.h b/llvm/utils/TableGen/Common/PredicateExpander.h
index 0c3a8718a473f..4439327af2b03 100644
--- a/llvm/utils/TableGen/Common/PredicateExpander.h
+++ b/llvm/utils/TableGen/Common/PredicateExpander.h
@@ -25,9 +25,9 @@ namespace llvm {
class Record;
class PredicateExpander {
- bool EmitCallsByRef;
- bool NegatePredicate;
- bool ExpandForMC;
+ bool EmitCallsByRef = true;
+ bool NegatePredicate = false;
+ bool ExpandForMC = false;
StringRef TargetName;
PredicateExpander(const PredicateExpander &) = delete;
@@ -38,8 +38,7 @@ class PredicateExpander {
public:
explicit PredicateExpander(StringRef Target, unsigned Indent = 1)
- : EmitCallsByRef(true), NegatePredicate(false), ExpandForMC(false),
- TargetName(Target), Indent(Indent, 2) {}
+ : TargetName(Target), Indent(Indent, 2) {}
bool isByRef() const { return EmitCallsByRef; }
bool shouldNegate() const { return NegatePredicate; }
bool shouldExpandForMC() const { return ExpandForMC; }
diff --git a/llvm/utils/TableGen/DAGISelMatcherGen.cpp b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
index 0039ff4f3e2d7..227311b0a3bc8 100644
--- a/llvm/utils/TableGen/DAGISelMatcherGen.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
@@ -76,7 +76,7 @@ class MatcherGen {
/// NextRecordedOperandNo - As we emit opcodes to record matched values in
/// the RecordedNodes array, this keeps track of which slot will be next to
/// record into.
- unsigned NextRecordedOperandNo;
+ unsigned NextRecordedOperandNo = 0;
/// MatchedChainNodes - This maintains the position in the recorded nodes
/// array of all of the recorded input nodes that have chains.
@@ -94,11 +94,11 @@ class MatcherGen {
SmallVector<std::pair<const Record *, unsigned>, 2> PhysRegInputs;
/// Matcher - This is the top level of the generated matcher, the result.
- Matcher *TheMatcher;
+ Matcher *TheMatcher = nullptr;
/// CurPredicate - As we emit matcher nodes, this points to the latest check
/// which should have future checks stuck into its Next position.
- Matcher *CurPredicate;
+ Matcher *CurPredicate = nullptr;
public:
MatcherGen(const PatternToMatch &pattern, const CodeGenDAGPatterns &cgp);
@@ -147,8 +147,7 @@ class MatcherGen {
MatcherGen::MatcherGen(const PatternToMatch &pattern,
const CodeGenDAGPatterns &cgp)
- : Pattern(pattern), CGP(cgp), NextRecordedOperandNo(0), TheMatcher(nullptr),
- CurPredicate(nullptr) {
+ : Pattern(pattern), CGP(cgp) {
// We need to produce the matcher tree for the patterns source pattern. To
// do this we need to match the structure as well as the types. To do the
// type matching, we want to figure out the fewest number of type checks we
diff --git a/llvm/utils/TableGen/DecoderEmitter.cpp b/llvm/utils/TableGen/DecoderEmitter.cpp
index 56c3644c134f1..7489d369c9932 100644
--- a/llvm/utils/TableGen/DecoderEmitter.cpp
+++ b/llvm/utils/TableGen/DecoderEmitter.cpp
@@ -104,10 +104,9 @@ struct OperandInfo {
std::vector<EncodingField> Fields;
std::string Decoder;
bool HasCompleteDecoder;
- uint64_t InitValue;
+ uint64_t InitValue = 0;
- OperandInfo(std::string D, bool HCD)
- : Decoder(D), HasCompleteDecoder(HCD), InitValue(0) {}
+ OperandInfo(std::string D, bool HCD) : Decoder(D), HasCompleteDecoder(HCD) {}
void addField(unsigned Base, unsigned Width, unsigned Offset) {
Fields.push_back(EncodingField(Base, Width, Offset));
diff --git a/llvm/utils/TableGen/FastISelEmitter.cpp b/llvm/utils/TableGen/FastISelEmitter.cpp
index a8b6f79c176a7..694d89a5ada3c 100644
--- a/llvm/utils/TableGen/FastISelEmitter.cpp
+++ b/llvm/utils/TableGen/FastISelEmitter.cpp
@@ -86,10 +86,10 @@ namespace {
struct OperandsSignature {
class OpKind {
enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 };
- char Repr;
+ char Repr = OK_Invalid;
public:
- OpKind() : Repr(OK_Invalid) {}
+ OpKind() {}
bool operator<(OpKind RHS) const { return Repr < RHS.Repr; }
bool operator==(OpKind RHS) const { return Repr == RHS.Repr; }
``````````
</details>
https://github.com/llvm/llvm-project/pull/144349
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