[llvm] [LV] Support strided load with a stride of -1 (PR #128718)

[Mel Chen via llvm-commits]

================
@@ -2523,6 +2529,78 @@ void VPlanTransforms::dissolveLoopRegions(VPlan &Plan) {
     R->dissolveToCFGLoop();
 }
 
+void VPlanTransforms::convertToStridedAccesses(VPlan &Plan, VPCostContext &Ctx,
+                                               VFRange &Range) {
+  if (Plan.hasScalarVFOnly())
+    return;
+
+  SmallVector<VPRecipeBase *> ToErase;
+  for (VPBasicBlock *VPBB : VPBlockUtils::blocksOnly<VPBasicBlock>(
+           vp_depth_first_shallow(Plan.getVectorLoopRegion()->getEntry()))) {
+    for (VPRecipeBase &R : make_early_inc_range(*VPBB)) {
+      auto *MemR = dyn_cast<VPWidenMemoryRecipe>(&R);
+      // TODO: support strided store
+      // TODO: support strided accesses with stride not equal to -1
+      if (!MemR || !isa<VPWidenLoadRecipe>(MemR) || !MemR->isReverse())
----------------
Mel-Chen wrote:

I think we don't have to check if MemR is consecutive. There is an assertion in constructor of VPWidenMemoryRecipe:
```
assert((Consecutive || !Reverse) && "Reverse implies consecutive");
```
So I add an assertion for consecutive.
72c17a195f0d58be93ebd405a6f09857102cf704

https://github.com/llvm/llvm-project/pull/128718