[llvm] [PowerPC] eliminate RLWINM instruction following LBARX as possible (PR #144089)

[via llvm-commits]

================
@@ -1281,7 +1281,40 @@ bool PPCMIPeephole::simplifyCode() {
         Simplified = true;
         break;
       }
-      case PPC::RLWINM:
+      case PPC::RLWINM: {
+        Register SrcReg = MI.getOperand(1).getReg();
+        MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
+
+        if (DefMI) {
+          unsigned Opcode = DefMI->getOpcode();
+          if (Opcode == PPC::LBARX || Opcode == PPC::LHARX) {
+            unsigned SH = MI.getOperand(2).getImm();
+            unsigned MB = MI.getOperand(3).getImm();
+            unsigned ME = MI.getOperand(4).getImm();
+
+            // LBARX already sets the upper 24 bits of the destination register
+            // to zero. If the register is cleared to zero in the upper 24 bits
+            // using RLWINM later, we eliminate the RLWINM. Same applies to
+            // LHARX.
----------------
RolandF77 wrote:

The ISA defines the opcodes in terms of 64-bit register bit positions, which is probably clearer. It's the upper 56 bits, 32-bit mode just can't see all of them. Also the bit numbers are different for lharx so saying the same applies is not quite right.

https://github.com/llvm/llvm-project/pull/144089