[llvm] b21be0e - [X86] scalarizeExtEltFP - don't assume setcc result pre-legalisation will be vXi1

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2025-06-10T14:58:20+01:00
New Revision: b21be0e440f18605b5ffbe9d0c44a55a50b91b4e

URL: https://github.com/llvm/llvm-project/commit/b21be0e440f18605b5ffbe9d0c44a55a50b91b4e
DIFF: https://github.com/llvm/llvm-project/commit/b21be0e440f18605b5ffbe9d0c44a55a50b91b4e.diff

LOG: [X86] scalarizeExtEltFP - don't assume setcc result pre-legalisation will be vXi1

Another fold may have generated the setcc using getSetCCResultType

Encountered this while investigating topological sorting of dag nodes

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 09a8276f59708..82427e826ee31 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -46802,9 +46802,8 @@ static SDValue scalarizeExtEltFP(SDNode *ExtElt, SelectionDAG &DAG,
   // need to convert vector bool to a scalar bool.
   if (DCI.isBeforeLegalize() && Vec.getOpcode() == ISD::VSELECT &&
       Vec.getOperand(0).getOpcode() == ISD::SETCC &&
-      Vec.getOperand(0).getOperand(0).getValueType() == VecVT) {
-    assert(Vec.getOperand(0).getValueType().getScalarType() == MVT::i1 &&
-           "Unexpected cond type for combine");
+      Vec.getOperand(0).getOperand(0).getValueType() == VecVT &&
+      Vec.getOperand(0).getValueType().getScalarType() == MVT::i1) {
     // ext (sel Cond, X, Y), 0 --> sel (ext Cond, 0), (ext X, 0), (ext Y, 0)
     SDLoc DL(ExtElt);
     SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,