[llvm] a08bf50 - [RISCV][NFC] Update the comments in RISCVMatInt.h (#143402)

[via llvm-commits]

Author: Piotr Fusik
Date: 2025-06-10T13:29:20+02:00
New Revision: a08bf50ccf95ab89a5e1252be87c4cf093ce3b60

URL: https://github.com/llvm/llvm-project/commit/a08bf50ccf95ab89a5e1252be87c4cf093ce3b60
DIFF: https://github.com/llvm/llvm-project/commit/a08bf50ccf95ab89a5e1252be87c4cf093ce3b60.diff

LOG: [RISCV][NFC] Update the comments in RISCVMatInt.h (#143402)

Only a subset of used instructions was listed, which could be confusing.
Also, QC_E_LI uses all 32 bits of Imm.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
index ae94f3778b217..a82cd650f42fa 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
@@ -20,15 +20,15 @@ class APInt;
 namespace RISCVMatInt {
 
 enum OpndKind {
-  RegImm, // ADDI/ADDIW/SLLI/SRLI/BSETI/BCLRI
-  Imm,    // LUI
-  RegReg, // SH1ADD/SH2ADD/SH3ADD
+  RegImm, // ADDI/ADDIW/XORI/SLLI/SRLI/SLLI_UW/RORI/BSETI/BCLRI/TH_SRRI
+  Imm,    // LUI/QC_LI/QC_E_LI
+  RegReg, // SH1ADD/SH2ADD/SH3ADD/PACK
   RegX0,  // ADD_UW
 };
 
 class Inst {
   unsigned Opc;
-  int32_t Imm; // The largest value we need to store is 20 bits.
+  int32_t Imm; // The largest value we need to store is 32 bits for QC_E_LI.
 
 public:
   Inst(unsigned Opc, int64_t I) : Opc(Opc), Imm(I) {