[llvm] 39a7664 - [RISCV] Select (add/or C, x) -> (add.uw C|0xffffffff00000000, x) (#143375)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 10 04:28:52 PDT 2025
Author: Piotr Fusik
Date: 2025-06-10T13:28:49+02:00
New Revision: 39a7664fc10d7634f0f8b8a320366221450cc790
URL: https://github.com/llvm/llvm-project/commit/39a7664fc10d7634f0f8b8a320366221450cc790
DIFF: https://github.com/llvm/llvm-project/commit/39a7664fc10d7634f0f8b8a320366221450cc790.diff
LOG: [RISCV] Select (add/or C, x) -> (add.uw C|0xffffffff00000000, x) (#143375)
Emits fewer instructions for certain constants.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
llvm/test/CodeGen/RISCV/rv64zba.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index babc0d7ab27e2..9ed67e74d440c 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3307,6 +3307,50 @@ bool RISCVDAGToDAGISel::selectSHXADD_UWOp(SDValue N, unsigned ShAmt,
return false;
}
+bool RISCVDAGToDAGISel::orIsAdd(const SDNode *N) const {
+ if (N->getFlags().hasDisjoint())
+ return true;
+ KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0);
+ KnownBits Known1 = CurDAG->computeKnownBits(N->getOperand(1), 0);
+ return KnownBits::haveNoCommonBitsSet(Known0, Known1);
+}
+
+bool RISCVDAGToDAGISel::selectImm64IfCheaper(int64_t Imm, int64_t OrigImm,
+ SDValue N, SDValue &Val) {
+ int OrigCost = RISCVMatInt::getIntMatCost(APInt(64, OrigImm), 64, *Subtarget,
+ /*CompressionCost=*/true);
+ int Cost = RISCVMatInt::getIntMatCost(APInt(64, Imm), 64, *Subtarget,
+ /*CompressionCost=*/true);
+ if (OrigCost <= Cost)
+ return false;
+
+ Val = selectImm(CurDAG, SDLoc(N), N->getSimpleValueType(0), Imm, *Subtarget);
+ return true;
+}
+
+bool RISCVDAGToDAGISel::selectZExtImm32(SDValue N, SDValue &Val) {
+ if (!isa<ConstantSDNode>(N))
+ return false;
+ int64_t Imm = cast<ConstantSDNode>(N)->getSExtValue();
+ if ((Imm >> 31) != 1)
+ return false;
+
+ for (const SDNode *U : N->users()) {
+ switch (U->getOpcode()) {
+ case ISD::ADD:
+ break;
+ case ISD::OR:
+ if (orIsAdd(U))
+ break;
+ return false;
+ default:
+ return false;
+ }
+ }
+
+ return selectImm64IfCheaper(0xffffffff00000000 | Imm, Imm, N, Val);
+}
+
bool RISCVDAGToDAGISel::selectNegImm(SDValue N, SDValue &Val) {
if (!isa<ConstantSDNode>(N))
return false;
@@ -3330,15 +3374,7 @@ bool RISCVDAGToDAGISel::selectNegImm(SDValue N, SDValue &Val) {
}
}
- int OrigImmCost = RISCVMatInt::getIntMatCost(APInt(64, Imm), 64, *Subtarget,
- /*CompressionCost=*/true);
- int NegImmCost = RISCVMatInt::getIntMatCost(APInt(64, -Imm), 64, *Subtarget,
- /*CompressionCost=*/true);
- if (OrigImmCost <= NegImmCost)
- return false;
-
- Val = selectImm(CurDAG, SDLoc(N), N->getSimpleValueType(0), -Imm, *Subtarget);
- return true;
+ return selectImm64IfCheaper(-Imm, Imm, N, Val);
}
bool RISCVDAGToDAGISel::selectInvLogicImm(SDValue N, SDValue &Val) {
@@ -3373,19 +3409,15 @@ bool RISCVDAGToDAGISel::selectInvLogicImm(SDValue N, SDValue &Val) {
}
}
- // For 64-bit constants, the instruction sequences get complex,
- // so we select inverted only if it's cheaper.
- if (!isInt<32>(Imm)) {
- int OrigImmCost = RISCVMatInt::getIntMatCost(APInt(64, Imm), 64, *Subtarget,
- /*CompressionCost=*/true);
- int NegImmCost = RISCVMatInt::getIntMatCost(APInt(64, ~Imm), 64, *Subtarget,
- /*CompressionCost=*/true);
- if (OrigImmCost <= NegImmCost)
- return false;
+ if (isInt<32>(Imm)) {
+ Val =
+ selectImm(CurDAG, SDLoc(N), N->getSimpleValueType(0), ~Imm, *Subtarget);
+ return true;
}
- Val = selectImm(CurDAG, SDLoc(N), N->getSimpleValueType(0), ~Imm, *Subtarget);
- return true;
+ // For 64-bit constants, the instruction sequences get complex,
+ // so we select inverted only if it's cheaper.
+ return selectImm64IfCheaper(~Imm, Imm, N, Val);
}
static bool vectorPseudoHasAllNBitUsers(SDNode *User, unsigned UserOpNo,
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index ccbba88378f73..abc0372d15c4f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -118,9 +118,11 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
return selectSHXADD_UWOp(N, ShAmt, Val);
}
+ bool selectZExtImm32(SDValue N, SDValue &Val);
bool selectNegImm(SDValue N, SDValue &Val);
bool selectInvLogicImm(SDValue N, SDValue &Val);
+ bool orIsAdd(const SDNode *Node) const;
bool hasAllNBitUsers(SDNode *Node, unsigned Bits,
const unsigned Depth = 0) const;
bool hasAllBUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 8); }
@@ -199,6 +201,8 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
bool doPeepholeMergeVVMFold();
bool doPeepholeNoRegPassThru();
bool performCombineVMergeAndVOps(SDNode *N);
+ bool selectImm64IfCheaper(int64_t Imm, int64_t OrigImm, SDValue N,
+ SDValue &Val);
};
class RISCVDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index b18a550b01912..0d1ff09f4da3a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1445,11 +1445,7 @@ def : PatGprUimmLog2XLen<sra, SRAI>;
// Select 'or' as ADDI if the immediate bits are known to be 0 in $rs1. This
// can improve compressibility.
def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
- if (N->getFlags().hasDisjoint())
- return true;
- KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0);
- KnownBits Known1 = CurDAG->computeKnownBits(N->getOperand(1), 0);
- return KnownBits::haveNoCommonBitsSet(Known0, Known1);
+ return orIsAdd(N);
}]>;
def : PatGprSimm12<or_is_add, ADDI>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 1da4adc8c3125..b54c2b042b4dd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -653,11 +653,7 @@ let HasOneUse = 1 in {
node:$E),
(riscv_or_vl node:$A, node:$B, node:$C,
node:$D, node:$E), [{
- if (N->getFlags().hasDisjoint())
- return true;
- KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0);
- KnownBits Known1 = CurDAG->computeKnownBits(N->getOperand(1), 0);
- return KnownBits::haveNoCommonBitsSet(Known0, Known1);
+ return orIsAdd(N);
}]>;
def riscv_sub_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D,
node:$E),
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 4353e94bdb1d0..4806bcc1d63de 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -704,9 +704,13 @@ def : CSImm12MulBy4Pat<SH2ADD>;
def : CSImm12MulBy8Pat<SH3ADD>;
} // Predicates = [HasStdExtZba]
+def zExtImm32 : ComplexPattern<i64, 1, "selectZExtImm32", [], [], 0>;
+
multiclass ADD_UWPat<Instruction add_uw> {
def : Pat<(i64 (add_like_non_imm12 (and GPR:$rs1, 0xFFFFFFFF), GPR:$rs2)),
(add_uw GPR:$rs1, GPR:$rs2)>;
+ def : Pat<(i64 (add_like zExtImm32:$rs1, GPR:$rs2)),
+ (add_uw zExtImm32:$rs1, GPR:$rs2)>;
def : Pat<(i64 (and GPR:$rs, 0xFFFFFFFF)), (add_uw GPR:$rs, (XLenVT X0))>;
}
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
index 4d93619262be7..fdff4a39932b9 100644
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -4260,10 +4260,11 @@ define i64 @add_u32simm32_zextw(i64 %x) nounwind {
;
; RV64XANDESPERF-LABEL: add_u32simm32_zextw:
; RV64XANDESPERF: # %bb.0: # %entry
+; RV64XANDESPERF-NEXT: li a1, -2
+; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a0, a1
; RV64XANDESPERF-NEXT: li a1, 1
; RV64XANDESPERF-NEXT: slli a1, a1, 32
; RV64XANDESPERF-NEXT: addi a1, a1, -2
-; RV64XANDESPERF-NEXT: add a0, a0, a1
; RV64XANDESPERF-NEXT: addi a1, a1, 1
; RV64XANDESPERF-NEXT: and a0, a0, a1
; RV64XANDESPERF-NEXT: ret
@@ -4413,12 +4414,24 @@ define ptr @udiv1280_gep(ptr %p, i16 zeroext %i) {
}
define i64 @adduw_m1(i64 %x) {
-; CHECK-LABEL: adduw_m1:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: srli a1, a1, 32
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: ret
+; RV64I-LABEL: adduw_m1:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a1, -1
+; RV64I-NEXT: srli a1, a1, 32
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: adduw_m1:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: li a1, -1
+; RV64ZBA-NEXT: add.uw a0, a1, a0
+; RV64ZBA-NEXT: ret
+;
+; RV64XANDESPERF-LABEL: adduw_m1:
+; RV64XANDESPERF: # %bb.0:
+; RV64XANDESPERF-NEXT: li a1, -1
+; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a0, a1
+; RV64XANDESPERF-NEXT: ret
%a = add i64 %x, 4294967295
ret i64 %a
}
@@ -4435,28 +4448,37 @@ define i64 @adduw_m3(i64 %x) {
; RV64ZBA-LABEL: adduw_m3:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: li a1, -3
-; RV64ZBA-NEXT: zext.w a1, a1
-; RV64ZBA-NEXT: add a0, a0, a1
+; RV64ZBA-NEXT: add.uw a0, a1, a0
; RV64ZBA-NEXT: ret
;
; RV64XANDESPERF-LABEL: adduw_m3:
; RV64XANDESPERF: # %bb.0:
-; RV64XANDESPERF-NEXT: li a1, 1
-; RV64XANDESPERF-NEXT: slli a1, a1, 32
-; RV64XANDESPERF-NEXT: addi a1, a1, -3
-; RV64XANDESPERF-NEXT: add a0, a0, a1
+; RV64XANDESPERF-NEXT: li a1, -3
+; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a0, a1
; RV64XANDESPERF-NEXT: ret
%a = add i64 %x, 4294967293
ret i64 %a
}
define i64 @adduw_3shl30(i64 %x) {
-; CHECK-LABEL: adduw_3shl30:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a1, 3
-; CHECK-NEXT: slli a1, a1, 30
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: ret
+; RV64I-LABEL: adduw_3shl30:
+; RV64I: # %bb.0:
+; RV64I-NEXT: li a1, 3
+; RV64I-NEXT: slli a1, a1, 30
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: adduw_3shl30:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: lui a1, 786432
+; RV64ZBA-NEXT: add.uw a0, a1, a0
+; RV64ZBA-NEXT: ret
+;
+; RV64XANDESPERF-LABEL: adduw_3shl30:
+; RV64XANDESPERF: # %bb.0:
+; RV64XANDESPERF-NEXT: lui a1, 786432
+; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a0, a1
+; RV64XANDESPERF-NEXT: ret
%a = add i64 %x, 3221225472
ret i64 %a
}
@@ -4475,19 +4497,16 @@ define i64 @adduw_m3_multiuse(i64 %x, i64 %y) {
; RV64ZBA-LABEL: adduw_m3_multiuse:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: li a2, -3
-; RV64ZBA-NEXT: zext.w a2, a2
-; RV64ZBA-NEXT: add a0, a0, a2
-; RV64ZBA-NEXT: add a1, a1, a2
+; RV64ZBA-NEXT: add.uw a0, a2, a0
+; RV64ZBA-NEXT: add.uw a1, a2, a1
; RV64ZBA-NEXT: or a0, a0, a1
; RV64ZBA-NEXT: ret
;
; RV64XANDESPERF-LABEL: adduw_m3_multiuse:
; RV64XANDESPERF: # %bb.0:
-; RV64XANDESPERF-NEXT: li a2, 1
-; RV64XANDESPERF-NEXT: slli a2, a2, 32
-; RV64XANDESPERF-NEXT: addi a2, a2, -3
-; RV64XANDESPERF-NEXT: add a0, a0, a2
-; RV64XANDESPERF-NEXT: add a1, a1, a2
+; RV64XANDESPERF-NEXT: li a2, -3
+; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a0, a2
+; RV64XANDESPERF-NEXT: nds.lea.b.ze a1, a1, a2
; RV64XANDESPERF-NEXT: or a0, a0, a1
; RV64XANDESPERF-NEXT: ret
%a = add i64 %x, 4294967293
@@ -4532,13 +4551,27 @@ define i64 @add_or_m3(i64 %x) {
}
define i64 @append_32ones(i64 %x) {
-; CHECK-LABEL: append_32ones:
-; CHECK: # %bb.0:
-; CHECK-NEXT: slli a0, a0, 32
-; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: srli a1, a1, 32
-; CHECK-NEXT: or a0, a0, a1
-; CHECK-NEXT: ret
+; RV64I-LABEL: append_32ones:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 32
+; RV64I-NEXT: li a1, -1
+; RV64I-NEXT: srli a1, a1, 32
+; RV64I-NEXT: or a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: append_32ones:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: slli a0, a0, 32
+; RV64ZBA-NEXT: li a1, -1
+; RV64ZBA-NEXT: add.uw a0, a1, a0
+; RV64ZBA-NEXT: ret
+;
+; RV64XANDESPERF-LABEL: append_32ones:
+; RV64XANDESPERF: # %bb.0:
+; RV64XANDESPERF-NEXT: slli a0, a0, 32
+; RV64XANDESPERF-NEXT: li a1, -1
+; RV64XANDESPERF-NEXT: nds.lea.b.ze a0, a0, a1
+; RV64XANDESPERF-NEXT: ret
%s = shl i64 %x, 32
%o = or i64 %s, 4294967295
ret i64 %o
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