[llvm] [RISCV][NFC] Update the comments in RISCVMatInt.h (PR #143402)
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Mon Jun 9 08:39:43 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Piotr Fusik (pfusik)
<details>
<summary>Changes</summary>
Only a subset of used instructions was listed, which could be confusing.
Also, QC_E_LI uses all 32 bits of Imm.
---
Full diff: https://github.com/llvm/llvm-project/pull/143402.diff
1 Files Affected:
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h (+4-4)
``````````diff
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
index ae94f3778b217..a82cd650f42fa 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
@@ -20,15 +20,15 @@ class APInt;
namespace RISCVMatInt {
enum OpndKind {
- RegImm, // ADDI/ADDIW/SLLI/SRLI/BSETI/BCLRI
- Imm, // LUI
- RegReg, // SH1ADD/SH2ADD/SH3ADD
+ RegImm, // ADDI/ADDIW/XORI/SLLI/SRLI/SLLI_UW/RORI/BSETI/BCLRI/TH_SRRI
+ Imm, // LUI/QC_LI/QC_E_LI
+ RegReg, // SH1ADD/SH2ADD/SH3ADD/PACK
RegX0, // ADD_UW
};
class Inst {
unsigned Opc;
- int32_t Imm; // The largest value we need to store is 20 bits.
+ int32_t Imm; // The largest value we need to store is 32 bits for QC_E_LI.
public:
Inst(unsigned Opc, int64_t I) : Opc(Opc), Imm(I) {
``````````
</details>
https://github.com/llvm/llvm-project/pull/143402
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