[llvm] [RISCV][NFC] Update the comments in RISCVMatInt.h (PR #143402)

[Piotr Fusik via llvm-commits]

https://github.com/pfusik created https://github.com/llvm/llvm-project/pull/143402

Only a subset of used instructions was listed, which could be confusing.
Also, QC_E_LI uses all 32 bits of Imm.

>From 40d90b962fec2e3b52fd9351ee95d24c518f1169 Mon Sep 17 00:00:00 2001
From: Piotr Fusik <p.fusik at samsung.com>
Date: Mon, 9 Jun 2025 17:37:20 +0200
Subject: [PATCH] [RISCV][NFC] Update the comments in RISCVMatInt.h

Only a subset of used instructions was listed, which could be confusing.
Also, QC_E_LI uses all 32 bits of Imm.
---
 llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
index ae94f3778b217..a82cd650f42fa 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
@@ -20,15 +20,15 @@ class APInt;
 namespace RISCVMatInt {
 
 enum OpndKind {
-  RegImm, // ADDI/ADDIW/SLLI/SRLI/BSETI/BCLRI
-  Imm,    // LUI
-  RegReg, // SH1ADD/SH2ADD/SH3ADD
+  RegImm, // ADDI/ADDIW/XORI/SLLI/SRLI/SLLI_UW/RORI/BSETI/BCLRI/TH_SRRI
+  Imm,    // LUI/QC_LI/QC_E_LI
+  RegReg, // SH1ADD/SH2ADD/SH3ADD/PACK
   RegX0,  // ADD_UW
 };
 
 class Inst {
   unsigned Opc;
-  int32_t Imm; // The largest value we need to store is 20 bits.
+  int32_t Imm; // The largest value we need to store is 32 bits for QC_E_LI.
 
 public:
   Inst(unsigned Opc, int64_t I) : Opc(Opc), Imm(I) {