[llvm] 432c5f2 - [TableGen] Use `emplace` instead of `insert` and similar. NFC. (#143164)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 7 01:32:40 PDT 2025
Author: Jay Foad
Date: 2025-06-07T09:32:36+01:00
New Revision: 432c5f2c608dfd40c4131e7e3a8282b0231b15ab
URL: https://github.com/llvm/llvm-project/commit/432c5f2c608dfd40c4131e7e3a8282b0231b15ab
DIFF: https://github.com/llvm/llvm-project/commit/432c5f2c608dfd40c4131e7e3a8282b0231b15ab.diff
LOG: [TableGen] Use `emplace` instead of `insert` and similar. NFC. (#143164)
Added:
Modified:
llvm/utils/TableGen/AsmWriterEmitter.cpp
llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
llvm/utils/TableGen/Common/CodeGenRegisters.cpp
llvm/utils/TableGen/Common/InfoByHwMode.cpp
llvm/utils/TableGen/Common/InfoByHwMode.h
llvm/utils/TableGen/Common/VarLenCodeEmitterGen.cpp
llvm/utils/TableGen/CompressInstEmitter.cpp
llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
llvm/utils/TableGen/InstrInfoEmitter.cpp
llvm/utils/TableGen/OptionParserEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp
index ebf1894b0d216..a3ea0f5e32e90 100644
--- a/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -1138,10 +1138,10 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
uint32_t UnescapedSize = 0;
std::string EncodedAsmString = IAP->formatAliasString(UnescapedSize);
auto Insertion =
- AsmStringOffsets.insert({EncodedAsmString, AsmStringsSize});
+ AsmStringOffsets.try_emplace(EncodedAsmString, AsmStringsSize);
if (Insertion.second) {
// If the string is new, add it to the vector.
- AsmStrings.push_back({AsmStringsSize, EncodedAsmString});
+ AsmStrings.emplace_back(AsmStringsSize, EncodedAsmString);
AsmStringsSize += UnescapedSize + 1;
}
unsigned AsmStrOffset = Insertion.first->second;
diff --git a/llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp b/llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
index 897788fe0f91e..2876a0e2ad546 100644
--- a/llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
+++ b/llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
@@ -728,7 +728,7 @@ void IntrinsicEmitter::EmitIntrinsicToBuiltinMap(
// Get the map for this target prefix.
auto &[Map, CommonPrefix] = BuiltinMap[Int.TargetPrefix];
- if (!Map.insert({BuiltinName, Int.EnumName}).second)
+ if (!Map.try_emplace(BuiltinName, Int.EnumName).second)
PrintFatalError(Int.TheDef->getLoc(),
"Intrinsic '" + Int.TheDef->getName() + "': duplicate " +
CompilerName + " builtin name!");
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index 2de2ecc46bc53..a87aa8b03d03d 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -147,7 +147,7 @@ bool TypeSetByHwMode::constrain(const TypeSetByHwMode &VTS) {
unsigned M = I.first;
if (M == DefaultMode || hasMode(M))
continue;
- Map.insert({M, Map.at(DefaultMode)});
+ Map.try_emplace(M, Map.at(DefaultMode));
Changed = true;
}
}
@@ -3297,14 +3297,14 @@ void CodeGenDAGPatterns::ParseNodeTransforms() {
reverse(Records.getAllDerivedDefinitions("SDNodeXForm"))) {
const Record *SDNode = XFormNode->getValueAsDef("Opcode");
StringRef Code = XFormNode->getValueAsString("XFormFunction");
- SDNodeXForms.insert({XFormNode, NodeXForm(SDNode, Code.str())});
+ SDNodeXForms.try_emplace(XFormNode, NodeXForm(SDNode, Code.str()));
}
}
void CodeGenDAGPatterns::ParseComplexPatterns() {
for (const Record *R :
reverse(Records.getAllDerivedDefinitions("ComplexPattern")))
- ComplexPatterns.insert({R, R});
+ ComplexPatterns.try_emplace(R, R);
}
/// ParsePatternFragments - Parse all of the PatFrag definitions in the .td
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index 3c8b3c5cc2929..8132f996e9632 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -466,7 +466,7 @@ void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
std::queue<std::pair<CodeGenSubRegIndex *, CodeGenRegister *>> SubRegQueue;
for (auto [SRI, SubReg] : SubRegs)
- SubRegQueue.push({SRI, SubReg});
+ SubRegQueue.emplace(SRI, SubReg);
// Look at the leading super-registers of each sub-register. Those are the
// candidates for new sub-registers, assuming they are fully contained in
@@ -1461,7 +1461,7 @@ void CodeGenRegBank::computeComposites() {
for (const CodeGenRegister &R : Registers) {
const CodeGenRegister::SubRegMap &SM = R.getSubRegs();
for (auto [SRI, SubReg] : SM)
- SubRegAction[SRI].insert({&R, SubReg});
+ SubRegAction[SRI].try_emplace(&R, SubReg);
}
// Calculate the composition of two subregisters as compositions of their
@@ -1474,7 +1474,7 @@ void CodeGenRegBank::computeComposites() {
for (auto [R, SubReg] : Img1) {
auto F = Img2.find(SubReg);
if (F != Img2.end())
- C.insert({R, F->second});
+ C.try_emplace(R, F->second);
}
return C;
};
diff --git a/llvm/utils/TableGen/Common/InfoByHwMode.cpp b/llvm/utils/TableGen/Common/InfoByHwMode.cpp
index c2368cb31dbbf..cb4f8876c648a 100644
--- a/llvm/utils/TableGen/Common/InfoByHwMode.cpp
+++ b/llvm/utils/TableGen/Common/InfoByHwMode.cpp
@@ -32,7 +32,7 @@ ValueTypeByHwMode::ValueTypeByHwMode(const Record *R,
const CodeGenHwModes &CGH) {
const HwModeSelect &MS = CGH.getHwModeSelect(R);
for (const HwModeSelect::PairType &P : MS.Items) {
- auto I = Map.insert({P.first, MVT(llvm::getValueType(P.second))});
+ auto I = Map.try_emplace(P.first, MVT(llvm::getValueType(P.second)));
assert(I.second && "Duplicate entry?");
(void)I;
}
@@ -142,7 +142,7 @@ RegSizeInfoByHwMode::RegSizeInfoByHwMode(const Record *R,
const CodeGenHwModes &CGH) {
const HwModeSelect &MS = CGH.getHwModeSelect(R);
for (const HwModeSelect::PairType &P : MS.Items) {
- auto I = Map.insert({P.first, RegSizeInfo(P.second)});
+ auto I = Map.try_emplace(P.first, RegSizeInfo(P.second));
assert(I.second && "Duplicate entry?");
(void)I;
}
@@ -195,7 +195,7 @@ SubRegRangeByHwMode::SubRegRangeByHwMode(const Record *R,
const CodeGenHwModes &CGH) {
const HwModeSelect &MS = CGH.getHwModeSelect(R);
for (const HwModeSelect::PairType &P : MS.Items) {
- auto I = Map.insert({P.first, SubRegRange(P.second)});
+ auto I = Map.try_emplace(P.first, SubRegRange(P.second));
assert(I.second && "Duplicate entry?");
(void)I;
}
@@ -207,7 +207,7 @@ EncodingInfoByHwMode::EncodingInfoByHwMode(const Record *R,
for (const HwModeSelect::PairType &P : MS.Items) {
assert(P.second && P.second->isSubClassOf("InstructionEncoding") &&
"Encoding must subclass InstructionEncoding");
- auto I = Map.insert({P.first, P.second});
+ auto I = Map.try_emplace(P.first, P.second);
assert(I.second && "Duplicate entry?");
(void)I;
}
diff --git a/llvm/utils/TableGen/Common/InfoByHwMode.h b/llvm/utils/TableGen/Common/InfoByHwMode.h
index bff164c6a6aa7..7925599a98a0c 100644
--- a/llvm/utils/TableGen/Common/InfoByHwMode.h
+++ b/llvm/utils/TableGen/Common/InfoByHwMode.h
@@ -118,7 +118,7 @@ template <typename InfoT> struct InfoByHwMode {
// Copy and insert the default mode which should be first.
assert(hasDefault());
- auto P = Map.insert({Mode, Map.begin()->second});
+ auto P = Map.try_emplace(Mode, Map.begin()->second);
return P.first->second;
}
const InfoT &get(unsigned Mode) const {
@@ -154,7 +154,7 @@ template <typename InfoT> struct InfoByHwMode {
struct ValueTypeByHwMode : public InfoByHwMode<MVT> {
ValueTypeByHwMode(const Record *R, const CodeGenHwModes &CGH);
ValueTypeByHwMode(const Record *R, MVT T);
- ValueTypeByHwMode(MVT T) { Map.insert({DefaultMode, T}); }
+ ValueTypeByHwMode(MVT T) { Map.try_emplace(DefaultMode, T); }
ValueTypeByHwMode() = default;
bool operator==(const ValueTypeByHwMode &T) const;
@@ -229,7 +229,9 @@ struct SubRegRange {
struct SubRegRangeByHwMode : public InfoByHwMode<SubRegRange> {
SubRegRangeByHwMode(const Record *R, const CodeGenHwModes &CGH);
- SubRegRangeByHwMode(SubRegRange Range) { Map.insert({DefaultMode, Range}); }
+ SubRegRangeByHwMode(SubRegRange Range) {
+ Map.try_emplace(DefaultMode, Range);
+ }
SubRegRangeByHwMode() = default;
void insertSubRegRangeForMode(unsigned Mode, SubRegRange Info) {
diff --git a/llvm/utils/TableGen/Common/VarLenCodeEmitterGen.cpp b/llvm/utils/TableGen/Common/VarLenCodeEmitterGen.cpp
index 9de6a585eb4de..e5e03b8bd8bd2 100644
--- a/llvm/utils/TableGen/Common/VarLenCodeEmitterGen.cpp
+++ b/llvm/utils/TableGen/Common/VarLenCodeEmitterGen.cpp
@@ -241,21 +241,21 @@ void VarLenCodeEmitterGen::run(raw_ostream &OS) {
const CodeGenHwModes &HWM = Target.getHwModes();
EncodingInfoByHwMode EBM(DI->getDef(), HWM);
for (const auto [Mode, EncodingDef] : EBM) {
- Modes.insert({Mode, "_" + HWM.getMode(Mode).Name.str()});
+ Modes.try_emplace(Mode, "_" + HWM.getMode(Mode).Name.str());
const RecordVal *RV = EncodingDef->getValue("Inst");
const DagInit *DI = cast<DagInit>(RV->getValue());
- VarLenInsts[R].insert({Mode, VarLenInst(DI, RV)});
+ VarLenInsts[R].try_emplace(Mode, VarLenInst(DI, RV));
}
continue;
}
}
const RecordVal *RV = R->getValue("Inst");
const DagInit *DI = cast<DagInit>(RV->getValue());
- VarLenInsts[R].insert({Universal, VarLenInst(DI, RV)});
+ VarLenInsts[R].try_emplace(Universal, VarLenInst(DI, RV));
}
if (Modes.empty())
- Modes.insert({Universal, ""}); // Base case, skip suffix.
+ Modes.try_emplace(Universal, ""); // Base case, skip suffix.
// Emit function declaration
OS << "void " << Target.getName()
diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp
index b981d38e283f3..4a0b6d79c53d9 100644
--- a/llvm/utils/TableGen/CompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/CompressInstEmitter.cpp
@@ -541,9 +541,9 @@ getReqFeatures(std::set<std::pair<bool, StringRef>> &FeaturesSet,
!cast<DefInit>(Arg)->getDef()->isSubClassOf("SubtargetFeature"))
PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
if (IsOr)
- AnyOfSet.insert({IsNot, cast<DefInit>(Arg)->getDef()->getName()});
+ AnyOfSet.emplace(IsNot, cast<DefInit>(Arg)->getDef()->getName());
else
- FeaturesSet.insert({IsNot, cast<DefInit>(Arg)->getDef()->getName()});
+ FeaturesSet.emplace(IsNot, cast<DefInit>(Arg)->getDef()->getName());
}
if (IsOr)
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index 13ab21630c695..49c33dc5ca149 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -151,7 +151,7 @@ class MatcherTableEmitter {
Uses += PredicateUsage[TP];
// We only add the first predicate here since they are with the same code.
- PredicateList.push_back({TPs[0], Uses});
+ PredicateList.emplace_back(TPs[0], Uses);
}
stable_sort(PredicateList, [](const auto &A, const auto &B) {
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index f240cab040caa..e72055b0b5037 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -203,7 +203,7 @@ InstrInfoEmitter::CollectOperandInfo(OperandInfoListTy &OperandInfoList,
unsigned Offset = 0;
for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
OperandInfoTy OperandInfo = GetOperandInfo(*Inst);
- if (OperandInfoMap.insert({OperandInfo, Offset}).second) {
+ if (OperandInfoMap.try_emplace(OperandInfo, Offset).second) {
OperandInfoList.push_back(OperandInfo);
Offset += OperandInfo.size();
}
@@ -503,7 +503,8 @@ void InstrInfoEmitter::emitLogicalOperandSizeMappings(
LogicalOpListSize = std::max(LogicalOpList.size(), LogicalOpListSize);
auto I =
- LogicalOpSizeMap.insert({LogicalOpList, LogicalOpSizeMap.size()}).first;
+ LogicalOpSizeMap.try_emplace(LogicalOpList, LogicalOpSizeMap.size())
+ .first;
InstMap[I->second].push_back(
(Namespace + "::" + Inst->TheDef->getName()).str());
}
@@ -850,7 +851,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
std::vector<const Record *> ImplicitOps = Inst->ImplicitUses;
llvm::append_range(ImplicitOps, Inst->ImplicitDefs);
- if (EmittedLists.insert({ImplicitOps, ImplicitListSize}).second) {
+ if (EmittedLists.try_emplace(ImplicitOps, ImplicitListSize).second) {
ImplicitLists.push_back(ImplicitOps);
ImplicitListSize += ImplicitOps.size();
}
diff --git a/llvm/utils/TableGen/OptionParserEmitter.cpp b/llvm/utils/TableGen/OptionParserEmitter.cpp
index 85b220070d1f3..f4964282934eb 100644
--- a/llvm/utils/TableGen/OptionParserEmitter.cpp
+++ b/llvm/utils/TableGen/OptionParserEmitter.cpp
@@ -264,11 +264,11 @@ static void emitOptionParser(const RecordKeeper &Records, raw_ostream &OS) {
typedef SmallVector<SmallString<2>, 2> PrefixKeyT;
typedef std::map<PrefixKeyT, unsigned> PrefixesT;
PrefixesT Prefixes;
- Prefixes.insert({PrefixKeyT(), 0});
+ Prefixes.try_emplace(PrefixKeyT(), 0);
for (const Record &R : llvm::make_pointee_range(Opts)) {
std::vector<StringRef> RPrefixes = R.getValueAsListOfStrings("Prefixes");
PrefixKeyT PrefixKey(RPrefixes.begin(), RPrefixes.end());
- Prefixes.insert({PrefixKey, 0});
+ Prefixes.try_emplace(PrefixKey, 0);
}
DenseSet<StringRef> PrefixesUnionSet;
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