[llvm] bb9dcb2 - [TableGen] Use `contains` instead of `count`. NFC. (#143156)
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Sat Jun 7 01:31:46 PDT 2025
Author: Jay Foad
Date: 2025-06-07T09:31:42+01:00
New Revision: bb9dcb27df133dd3788e7dfcd2bf31382673a2bc
URL: https://github.com/llvm/llvm-project/commit/bb9dcb27df133dd3788e7dfcd2bf31382673a2bc
DIFF: https://github.com/llvm/llvm-project/commit/bb9dcb27df133dd3788e7dfcd2bf31382673a2bc.diff
LOG: [TableGen] Use `contains` instead of `count`. NFC. (#143156)
Added:
Modified:
llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
llvm/utils/TableGen/Common/CodeGenRegisters.cpp
llvm/utils/TableGen/Common/CodeGenSchedule.cpp
llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
llvm/utils/TableGen/Common/GlobalISel/Patterns.cpp
llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/utils/TableGen/Basic/DirectiveEmitter.cpp b/llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
index ac166a1db4aff..177eecebce9a5 100644
--- a/llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
+++ b/llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
@@ -685,7 +685,8 @@ static void emitLeafTable(const DirectiveLanguage &DirLang, raw_ostream &OS,
auto &LeavesB = LeafTable[B];
int DirA = LeavesA[0], DirB = LeavesB[0];
// First of all, end directives compare greater than non-end directives.
- int IsEndA = EndDirectives.count(DirA), IsEndB = EndDirectives.count(DirB);
+ bool IsEndA = EndDirectives.contains(DirA);
+ bool IsEndB = EndDirectives.contains(DirB);
if (IsEndA != IsEndB)
return IsEndA < IsEndB;
if (LeavesA[1] == 0 && LeavesB[1] == 0)
@@ -725,7 +726,7 @@ static void emitLeafTable(const DirectiveLanguage &DirLang, raw_ostream &OS,
// Emit a marker where the first "end directive" is.
auto FirstE = find_if(Ordering, [&](int RowIdx) {
- return EndDirectives.count(LeafTable[RowIdx][0]);
+ return EndDirectives.contains(LeafTable[RowIdx][0]);
});
OS << "[[maybe_unused]] static auto " << TableName
<< "EndDirective = " << TableName << " + "
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index 3029604adcc36..2de2ecc46bc53 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -730,8 +730,8 @@ bool TypeInfer::EnforceSameNumElts(TypeSetByHwMode &V, TypeSetByHwMode &W) {
// processed identically.
auto NoLength = [](const SmallDenseSet<ElementCount> &Lengths,
MVT T) -> bool {
- return !Lengths.count(T.isVector() ? T.getVectorElementCount()
- : ElementCount());
+ return !Lengths.contains(T.isVector() ? T.getVectorElementCount()
+ : ElementCount());
};
SmallVector<unsigned, 4> Modes;
@@ -778,7 +778,7 @@ bool TypeInfer::EnforceSameSize(TypeSetByHwMode &A, TypeSetByHwMode &B) {
typedef SmallSet<TypeSize, 2, TypeSizeComparator> TypeSizeSet;
auto NoSize = [](const TypeSizeSet &Sizes, MVT T) -> bool {
- return !Sizes.count(T.getSizeInBits());
+ return !Sizes.contains(T.getSizeInBits());
};
SmallVector<unsigned, 4> Modes;
@@ -3331,7 +3331,7 @@ void CodeGenDAGPatterns::ParsePatternFragments(bool OutFrags) {
auto ArgsCopy = Args;
SmallDenseSet<StringRef, 4> OperandsSet(llvm::from_range, ArgsCopy);
- if (OperandsSet.count(""))
+ if (OperandsSet.contains(""))
P->error("Cannot have unnamed 'node' values in pattern fragment!");
// Parse the operands list.
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index a23222aa555aa..3c8b3c5cc2929 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -1532,7 +1532,7 @@ void CodeGenRegBank::computeComposites() {
if (CodeGenSubRegIndex *Prev =
Idx1->addComposite(Idx2, Idx3, getHwModes())) {
// If the composition was not user-defined, always emit a warning.
- if (!UserDefined.count({Idx1, Idx2}) ||
+ if (!UserDefined.contains({Idx1, Idx2}) ||
agree(compose(Idx1, Idx2), SubRegAction.at(Idx3)))
PrintWarning(Twine("SubRegIndex ") + Idx1->getQualifiedName() +
" and " + Idx2->getQualifiedName() +
@@ -2408,7 +2408,7 @@ void CodeGenRegBank::inferMatchingSuperRegClass(
if (RC->getSubClassWithSubReg(SubIdx) != RC)
continue;
- if (ImpliedSubRegIndices.count(SubIdx))
+ if (ImpliedSubRegIndices.contains(SubIdx))
continue;
// Build list of (Sub, Super) pairs for this SubIdx, sorted by Sub. Note
@@ -2639,13 +2639,13 @@ CodeGenRegBank::computeCoveredRegisters(ArrayRef<const Record *> Regs) {
// Second, find all super-registers that are completely covered by the set.
for (unsigned i = 0; i != Set.size(); ++i) {
for (const CodeGenRegister *Super : Set[i]->getSuperRegs()) {
- if (!Super->CoveredBySubRegs || Set.count(Super))
+ if (!Super->CoveredBySubRegs || Set.contains(Super))
continue;
// This new super-register is covered by its sub-registers.
bool AllSubsInSet = true;
const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs();
for (auto [_, SR] : SRM)
- if (!Set.count(SR)) {
+ if (!Set.contains(SR)) {
AllSubsInSet = false;
break;
}
diff --git a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
index 8cd8fb6ba90c1..72954804b66f8 100644
--- a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
@@ -1637,7 +1637,7 @@ static void inferFromTransitions(ArrayRef<PredTransition> LastTransitions,
// Transition should not contain processor indices already assigned to
// InstRWs in this scheduling class.
const CodeGenSchedClass &FromSC = SchedModels.getSchedClass(FromClassIdx);
- if (FromSC.InstRWProcIndices.count(LastTransition.ProcIndex))
+ if (FromSC.InstRWProcIndices.contains(LastTransition.ProcIndex))
continue;
SCTrans.ProcIndex = LastTransition.ProcIndex;
SCTrans.ToClassIdx =
@@ -2176,7 +2176,7 @@ bool CodeGenProcModel::isUnsupported(const CodeGenInstruction &Inst) const {
}
bool CodeGenProcModel::hasReadOfWrite(const Record *WriteDef) const {
- return ReadOfWriteSet.count(WriteDef);
+ return ReadOfWriteSet.contains(WriteDef);
}
#ifndef NDEBUG
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
index 9f17882cdae4f..fd2445965fce7 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
@@ -1400,7 +1400,7 @@ class InstructionOpcodeMatcher : public InstructionPredicateMatcher {
}
bool hasValue() const override {
- return Insts.size() == 1 && OpcodeValues.count(Insts[0]);
+ return Insts.size() == 1 && OpcodeValues.contains(Insts[0]);
}
// TODO: This is used for the SwitchMatcher optimization. We should be able to
diff --git a/llvm/utils/TableGen/Common/GlobalISel/Patterns.cpp b/llvm/utils/TableGen/Common/GlobalISel/Patterns.cpp
index 981761821300e..07db6baef84a0 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/Patterns.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/Patterns.cpp
@@ -581,7 +581,7 @@ bool PatFrag::checkSemantics() {
StringSet<> SeenOps;
for (const auto &Op : in_params()) {
- if (SeenOps.count(Op.Name)) {
+ if (SeenOps.contains(Op.Name)) {
PrintError("duplicate parameter '" + Op.Name + "'");
return false;
}
@@ -609,7 +609,7 @@ bool PatFrag::checkSemantics() {
return false;
}
- if (SeenOps.count(Op.Name)) {
+ if (SeenOps.contains(Op.Name)) {
PrintError("duplicate parameter '" + Op.Name + "'");
return false;
}
diff --git a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
index 090e6bb37c3aa..afaf0507d904e 100644
--- a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
@@ -1161,7 +1161,7 @@ bool CombineRuleBuilder::buildPermutationsToEmit() {
PermutationsToEmit.clear();
for (const auto &Perm : CurPerms) {
- assert(!Perm.count(Pat.get()) && "Pattern already emitted?");
+ assert(!Perm.contains(Pat.get()) && "Pattern already emitted?");
for (unsigned K = 0; K < NumAlts; ++K) {
PatternAlternatives NewPerm = Perm;
NewPerm[Pat.get()] = K;
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