[llvm] [RISCV] Select unsigned bitfield insert for XAndesPerf (PR #142737)

[Jim Lin via llvm-commits]

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@@ -688,6 +688,23 @@ bool RISCVDAGToDAGISel::tryUnsignedBitfieldExtract(SDNode *Node, SDLoc DL,
   return true;
 }
 
+bool RISCVDAGToDAGISel::tryUnsignedBitfieldInsertInZero(SDNode *Node, SDLoc DL,
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tclin914 wrote:

Agree with @lenary's point and have updated the lsb/msb arguments/variables to accurately represent the least significant bit and most significant bit of the insertion.

https://github.com/llvm/llvm-project/pull/142737