[llvm] AMDGPU: Add test showing bit operations that should be reducible (PR #141837)

[Jay Foad via llvm-commits]

================
@@ -0,0 +1,162 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
+
+; Check for situations where we could reduce the width of bitwise
+; operations.
+
+
+; Should be able to reduce this to a 32-bit or plus a copy
+; https://alive2.llvm.org/ce/z/9LddFX
+define i64 @v_xor_i64_known_hi_i32_from_arg_range(i64 range(i64 0, 4294967296) %arg0, i64 %arg1) {
+; CHECK-LABEL: v_xor_i64_known_hi_i32_from_arg_range:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v3
+; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v2
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %xor = xor i64 %arg0, %arg1
+  ret i64 %xor
+}
+
+; Should be able to reduce this to a 32-bit or plus a copy
+; https://alive2.llvm.org/ce/z/HaXnBJ
+define i64 @v_or_i64_known_hi_i32_from_arg_range(i64 range(i64 0, 4294967296) %arg0, i64 %arg1) {
+; CHECK-LABEL: v_or_i64_known_hi_i32_from_arg_range:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_or_b32_e32 v1, v1, v3
+; CHECK-NEXT:    v_or_b32_e32 v0, v0, v2
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %or = or i64 %arg0, %arg1
+  ret i64 %or
+}
+
+; https://alive2.llvm.org/ce/z/M96Ror
+; Should be able to reduce this to a 32-bit plus a copy
----------------
jayfoad wrote:

```suggestion
; Should be able to reduce this to a 32-bit and plus a copy
```

https://github.com/llvm/llvm-project/pull/141837