[llvm] [AMDGPU][MC] Allow op_sel in v_alignbit_b32 etc in GFX9 and GFX10 (PR #142188)

[Jun Wang via llvm-commits]

jwanggit86 wrote:

> How do you intend to address the fact that some versions of gfx9 and gfx10 claim to op_sel and some do not?

Where can I find this in the specs?

> What will the behavior be when op_sel is applied to 32 bit registers?

It's not clear from the documents. Maybe 0 for lower half and 1 for higher half?
 
> The issue you claim #38650 only suggests the op_sel might be supported, it is not a justification. How can this new support be used?

This was mainly done from the assembler's point of view. Opsel is not allowed in those two instructions, but the docs seem to indicate it should be.


https://github.com/llvm/llvm-project/pull/142188