[llvm] [SwitchLowering] Support merging 0 and power-of-2 case. (PR #139736)

[Amara Emerson via llvm-commits]

================
@@ -931,7 +931,14 @@ void IRTranslator::emitSwitchCase(SwitchCG::CaseBlock &CB,
 
   const LLT i1Ty = LLT::scalar(1);
   // Build the compare.
-  if (!CB.CmpMHS) {
+  if (CB.EmitAnd) {
+    const LLT Ty = getLLTForType(*CB.CmpRHS->getType(), *DL);
+    Register CondLHS = getOrCreateVReg(*CB.CmpLHS);
+    Register C = getOrCreateVReg(*CB.CmpRHS);
+    Register And = MIB.buildAnd(Ty, CondLHS, C).getReg(0);
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aemerson wrote:

```suggestion
    auto And = MIB.buildAnd(ty, CondLHS, C);
```

https://github.com/llvm/llvm-project/pull/139736