[llvm] [AArch64] TableGen-erate SDNode descriptions (PR #140472)

[Sergei Barannikov via llvm-commits]

================
@@ -1049,6 +1128,68 @@ def AArch64rshrnb_pf : PatFrags<(ops node:$rs, node:$i),
 def AArch64CttzElts : SDNode<"AArch64ISD::CTTZ_ELTS", SDTypeProfile<1, 1,
                              [SDTCisInt<0>, SDTCisVec<1>]>, []>;
 
+// NEON Load/Store with post-increment base updates.
+// TODO: Complete SDTypeProfile constraints.
+def AArch64ld2post : SDNode<"AArch64ISD::LD2post", SDTypeProfile<3, 2, []>, [
+    SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
----------------
s-barannikov wrote:

The most common style is:
```suggestion
def AArch64ld2post : SDNode<"AArch64ISD::LD2post", SDTypeProfile<3, 2, []>,
                            [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
```

https://github.com/llvm/llvm-project/pull/140472