[llvm] [AArch64] TableGen-erate SDNode descriptions (PR #140472)

[Benjamin Maxwell via llvm-commits]

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@@ -1,12 +1,11 @@
-//===- llvm/unittest/CodeGen/AArch64SelectionDAGTest.cpp -------------------------===//
-//
+//===----------------------------------------------------------------------===//
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MacDue wrote:

IIUC it used to be a requirement; however, the coding guidelines have since removed it: https://llvm.org/docs/CodingStandards.html#file-headers

https://github.com/llvm/llvm-project/pull/140472