[llvm] [AArch64] TableGen-erate SDNode descriptions (PR #140472)

[Paul Walker via llvm-commits]

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@@ -23,22 +27,15 @@ static cl::opt<bool>
                                 "to lower to librt functions"),
                        cl::init(true));
 
-bool AArch64SelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
-  return Opcode >= AArch64ISD::FIRST_MEMORY_OPCODE &&
-         Opcode <= AArch64ISD::LAST_MEMORY_OPCODE;
-}
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paulwalker-arm wrote:

I see. Thanks.

https://github.com/llvm/llvm-project/pull/140472