[llvm] [AArch64] TableGen-erate SDNode descriptions (PR #140472)
Paul Walker via llvm-commits
llvm-commits at lists.llvm.org
Tue May 27 04:18:26 PDT 2025
================
@@ -1,12 +1,11 @@
-//===- llvm/unittest/CodeGen/AArch64SelectionDAGTest.cpp -------------------------===//
-//
+//===----------------------------------------------------------------------===//
----------------
paulwalker-arm wrote:
I see. Thanks.
https://github.com/llvm/llvm-project/pull/140472
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