[llvm] [AArch64] TableGen-erate SDNode descriptions (PR #140472)
Benjamin Maxwell via llvm-commits
llvm-commits at lists.llvm.org
Tue May 27 04:17:30 PDT 2025
================
@@ -23,22 +27,15 @@ static cl::opt<bool>
"to lower to librt functions"),
cl::init(true));
-bool AArch64SelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
- return Opcode >= AArch64ISD::FIRST_MEMORY_OPCODE &&
- Opcode <= AArch64ISD::LAST_MEMORY_OPCODE;
-}
----------------
MacDue wrote:
It's based on whether the node has the `SDNPMemOperand` property or not.
https://github.com/llvm/llvm-project/pull/140472
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