[llvm] [WIP][SDAG] Add partial_reduce_sumla node (PR #141267)

[Sander de Smalen via llvm-commits]

https://github.com/sdesmalen-arm commented:

Questions to the AArch64 folks:

> * Does aarch64 have a good implementation for this that I missed?
There is the USDOT instruction, which does a dot-product by zero-extending the LHS and sign-extending the RHS.

> * If not, any suggestions on how to structure splitting the legalization table? I could add the opcode to the table key; that's probably the easiest.
For AArch64 there is (zext, zext), (sext, sext), (zext, sext) (and because the operation is commutative (sext, zext) as well). We need to encode this in the table somehow, because a different set of types are supported for the mixed extends.

https://github.com/llvm/llvm-project/pull/141267