[llvm] [LoongArch] Enable interleaved memory accesses by default (PR #141555)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-loongarch

Author: None (tangaac)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/141555.diff


1 Files Affected:

- (modified) llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h (+1) 


``````````diff
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h b/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
index d43d2cb0eb124..dc0478daeb6af 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
@@ -52,6 +52,7 @@ class LoongArchTTIImpl : public BasicTTIImplBase<LoongArchTTIImpl> {
   unsigned getCacheLineSize() const override;
   unsigned getPrefetchDistance() const override;
   bool enableWritePrefetching() const override;
+  bool enableInterleavedAccessVectorization() const override { return true; }
 
   // TODO: Implement more hooks to provide TTI machinery for LoongArch.
 };

``````````

</details>


https://github.com/llvm/llvm-project/pull/141555