[llvm] [LoongArch] Enable interleaved memory accesses by default (PR #141555)

[via llvm-commits]

https://github.com/tangaac created https://github.com/llvm/llvm-project/pull/141555

None

>From 183912466280a46b92ec107910355a8ad0707cee Mon Sep 17 00:00:00 2001
From: tangaac <tangyan01 at loongson.cn>
Date: Tue, 27 May 2025 14:47:22 +0800
Subject: [PATCH] Enable interleaved memory accesses by default

---
 llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h b/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
index d43d2cb0eb124..dc0478daeb6af 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.h
@@ -52,6 +52,7 @@ class LoongArchTTIImpl : public BasicTTIImplBase<LoongArchTTIImpl> {
   unsigned getCacheLineSize() const override;
   unsigned getPrefetchDistance() const override;
   bool enableWritePrefetching() const override;
+  bool enableInterleavedAccessVectorization() const override { return true; }
 
   // TODO: Implement more hooks to provide TTI machinery for LoongArch.
 };