[llvm] [AArch64] Extend usage of `XAR` instruction for fixed-length operations (PR #139460)

[Rajveer Singh Bharadwaj via llvm-commits]

https://github.com/Rajveer100 updated https://github.com/llvm/llvm-project/pull/139460

>From 0783f5dfd06d2605da936b21ca8be9567f340238 Mon Sep 17 00:00:00 2001
From: Rajveer <rajveer.developer at icloud.com>
Date: Sun, 11 May 2025 22:27:50 +0530
Subject: [PATCH] [AArch64] Extend usage of `XAR` instruction for fixed-length
 operations

Resolves #139229

In #137162, support for `v2i64` was implemented for vector rotate
transformation, although types like `v4i32`, `v8i16` and `v16i8`
do not have Neon SHA3, we can use SVE operations if sve2-sha3
is available.
---
 llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 96fa85179d023..188cb76e21c30 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -4632,19 +4632,27 @@ bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) {
   SDValue Imm = CurDAG->getTargetConstant(
       ShAmt, DL, N0.getOperand(1).getValueType(), false);
 
-  if (ShAmt + HsAmt != 64)
+  if (ShAmt + HsAmt != VT.getScalarSizeInBits())
     return false;
 
   if (!IsXOROperand) {
     SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i64);
     SDNode *MOV = CurDAG->getMachineNode(AArch64::MOVIv2d_ns, DL, VT, Zero);
     SDValue MOVIV = SDValue(MOV, 0);
-    R1 = N1->getOperand(0);
+
+    SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, VT), 0);
+    R1 = CurDAG->getTargetInsertSubreg(AArch64::zsub, DL, VT, Undef, N1->getOperand(0));
+
+    // R1 = N1->getOperand(0);
     R2 = MOVIV;
   }
 
   SDValue Ops[] = {R1, R2, Imm};
-  CurDAG->SelectNodeTo(N, AArch64::XAR, N0.getValueType(), Ops);
+  SDValue Xar = SDValue(CurDAG->SelectNodeTo(N, AArch64::XAR, N0.getValueType(), Ops), 0);
+
+  SDValue ExtractSubReg =
+      CurDAG->getTargetExtractSubreg(AArch64::zsub, DL, VT, Xar);
+  ReplaceUses(N1, ExtractSubReg);
 
   return true;
 }