[llvm] [IR] Add llvm `clmul` intrinsic (PR #140301)
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Sun May 25 05:11:54 PDT 2025
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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
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git-clang-format --diff HEAD~1 HEAD --extensions h,cpp -- llvm/include/llvm/CodeGen/ISDOpcodes.h llvm/include/llvm/CodeGen/TargetLowering.h llvm/lib/CodeGen/IntrinsicLowering.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/lib/CodeGen/TargetLoweringBase.cpp llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h
index fc3b3b26c..589fb4522 100644
--- a/llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -751,7 +751,7 @@ enum NodeType {
ROTR,
FSHL,
FSHR,
-
+
/// Carryless multiplication operator
CLMUL,
diff --git a/llvm/lib/CodeGen/IntrinsicLowering.cpp b/llvm/lib/CodeGen/IntrinsicLowering.cpp
index 9111790e0..09ac7ce20 100644
--- a/llvm/lib/CodeGen/IntrinsicLowering.cpp
+++ b/llvm/lib/CodeGen/IntrinsicLowering.cpp
@@ -200,7 +200,8 @@ static Value *LowerCTLZ(LLVMContext &Context, Value *V, Instruction *IP) {
}
/// Emit the code to lower clmul of V1, V2 before the specified instruction IP.
-static Value *LowerCLMUL(LLVMContext &Context, Value *V1, Value *V2, Instruction *IP) {
+static Value *LowerCLMUL(LLVMContext &Context, Value *V1, Value *V2,
+ Instruction *IP) {
IRBuilder<> Builder(IP);
@@ -282,7 +283,8 @@ void IntrinsicLowering::LowerIntrinsicCall(CallInst *CI) {
break;
case Intrinsic::clmul:
- CI->replaceAllUsesWith(LowerCLMUL(Context, CI->getArgOperand(0), CI->getArgOperand(1), CI));
+ CI->replaceAllUsesWith(
+ LowerCLMUL(Context, CI->getArgOperand(0), CI->getArgOperand(1), CI));
break;
case Intrinsic::cttz: {
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 3b5a8bf5c..dd6c8ebbc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -208,7 +208,9 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::VP_ADD:
case ISD::VP_SUB:
case ISD::VP_MUL:
- case ISD::CLMUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
+ case ISD::CLMUL:
+ Res = PromoteIntRes_SimpleIntBinOp(N);
+ break;
case ISD::ABDS:
case ISD::AVGCEILS:
@@ -5422,15 +5424,14 @@ void DAGTypeLegalizer::ExpandIntRes_FunnelShift(SDNode *N, SDValue &Lo,
Hi = DAG.getNode(Opc, DL, HalfVT, Select3, Select2, NewShAmt);
}
-void DAGTypeLegalizer::ExpandIntRes_CLMUL(SDNode *N, SDValue &Lo,
- SDValue &Hi) {
+void DAGTypeLegalizer::ExpandIntRes_CLMUL(SDNode *N, SDValue &Lo, SDValue &Hi) {
// Values numbered from least significant to most significant.
SDValue LL, LH, RL, RH;
GetExpandedInteger(N->getOperand(0), LL, LH);
GetExpandedInteger(N->getOperand(1), RL, RH);
EVT HalfVT = LL.getValueType();
SDLoc DL(N);
-
+
// CLMUL is carryless so Lo is computed from the low half
Lo = DAG.getNode(ISD::CLMUL, DL, HalfVT, LL, RL);
// the high bits not included in CLMUL(A,B) can be computed by
@@ -5438,14 +5439,15 @@ void DAGTypeLegalizer::ExpandIntRes_CLMUL(SDNode *N, SDValue &Lo,
// Therefore we can compute the 2 hi/lo cross products
// and the the overflow of the low product
// and xor them together to compute HI
- // TODO: if the target supports a widening CLMUL or a CLMULH we should probably use that
+ // TODO: if the target supports a widening CLMUL or a CLMULH we should
+ // probably use that
SDValue BitRevLL = DAG.getNode(ISD::BITREVERSE, DL, HalfVT, LL);
SDValue BitRevRL = DAG.getNode(ISD::BITREVERSE, DL, HalfVT, RL);
SDValue BitRevLoHi = DAG.getNode(ISD::CLMUL, DL, HalfVT, BitRevLL, BitRevRL);
SDValue LoHi = DAG.getNode(ISD::BITREVERSE, DL, HalfVT, BitRevLoHi);
SDValue One = DAG.getShiftAmountConstant(1, HalfVT, DL);
Hi = DAG.getNode(ISD::SRL, DL, HalfVT, LoHi, One);
-
+
SDValue HITMP = DAG.getNode(ISD::CLMUL, DL, HalfVT, LL, RH);
Hi = DAG.getNode(ISD::XOR, DL, HalfVT, Hi, HITMP);
HITMP = DAG.getNode(ISD::CLMUL, DL, HalfVT, LH, RL);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 255a587cb..51f887295 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -508,7 +508,7 @@ private:
void ExpandIntRes_Rotate (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_FunnelShift (SDNode *N, SDValue &Lo, SDValue &Hi);
- void ExpandIntRes_CLMUL (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_CLMUL(SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_VSCALE (SDNode *N, SDValue &Lo, SDValue &Hi);
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index d32a68fb7..76bedcbb3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -8131,8 +8131,7 @@ SDValue TargetLowering::expandFunnelShift(SDNode *Node,
return DAG.getNode(ISD::OR, DL, VT, ShX, ShY);
}
-SDValue TargetLowering::expandCLMUL(SDNode *Node,
- SelectionDAG &DAG) const {
+SDValue TargetLowering::expandCLMUL(SDNode *Node, SelectionDAG &DAG) const {
SDLoc DL(Node);
EVT VT = Node->getValueType(0);
SDValue V1 = Node->getOperand(0);
@@ -8146,10 +8145,10 @@ SDValue TargetLowering::expandCLMUL(SDNode *Node,
// subvector.
if (VT.isVector() && (!isPowerOf2_32(NumBitsPerElt) ||
(!isOperationLegalOrCustom(ISD::SRL, VT) ||
- !isOperationLegalOrCustom(ISD::SHL, VT) ||
- !isOperationLegalOrCustom(ISD::XOR, VT) ||
- !isOperationLegalOrCustom(ISD::AND, VT) ||
- !isOperationLegalOrCustom(ISD::SELECT, VT))))
+ !isOperationLegalOrCustom(ISD::SHL, VT) ||
+ !isOperationLegalOrCustom(ISD::XOR, VT) ||
+ !isOperationLegalOrCustom(ISD::AND, VT) ||
+ !isOperationLegalOrCustom(ISD::SELECT, VT))))
return DAG.UnrollVectorOp(Node);
SDValue Res = DAG.getConstant(0, DL, VT);
``````````
</details>
https://github.com/llvm/llvm-project/pull/140301
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