[llvm] [RISCV] Move RISCVIndirectBranchTracking before Branch Relaxation (PR #139993)
Jesse Huang via llvm-commits
llvm-commits at lists.llvm.org
Sun May 25 04:26:24 PDT 2025
https://github.com/jaidTw updated https://github.com/llvm/llvm-project/pull/139993
>From 06f4e7d9755ddbbb9b53fdbe613cbf3d5456fd08 Mon Sep 17 00:00:00 2001
From: Jesse Huang <jesse.huang at sifive.com>
Date: Mon, 5 May 2025 03:40:30 -0700
Subject: [PATCH 1/3] [RISCV] Move RISCVIndirectBranchTracking before Branch
Relaxation
---
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 2 +-
llvm/test/CodeGen/RISCV/O0-pipeline.ll | 2 +-
llvm/test/CodeGen/RISCV/O3-pipeline.ll | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 7fb64be3975d5..28283c9fd5b6d 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -570,6 +570,7 @@ void RISCVPassConfig::addPreEmitPass() {
addPass(createMachineCopyPropagationPass(true));
if (TM->getOptLevel() >= CodeGenOptLevel::Default)
addPass(createRISCVLateBranchOptPass());
+ addPass(createRISCVIndirectBranchTrackingPass());
addPass(&BranchRelaxationPassID);
addPass(createRISCVMakeCompressibleOptPass());
}
@@ -581,7 +582,6 @@ void RISCVPassConfig::addPreEmitPass2() {
// ensuring return instruction is detected correctly.
addPass(createRISCVPushPopOptimizationPass());
}
- addPass(createRISCVIndirectBranchTrackingPass());
addPass(createRISCVExpandPseudoPass());
// Schedule the expansion of AMOs at the last possible moment, avoiding the
diff --git a/llvm/test/CodeGen/RISCV/O0-pipeline.ll b/llvm/test/CodeGen/RISCV/O0-pipeline.ll
index 694662eab1681..8714b286374a5 100644
--- a/llvm/test/CodeGen/RISCV/O0-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O0-pipeline.ll
@@ -62,6 +62,7 @@
; CHECK-NEXT: Insert fentry calls
; CHECK-NEXT: Insert XRay ops
; CHECK-NEXT: Implement the 'patchable-function' attribute
+; CHECK-NEXT: RISC-V Indirect Branch Tracking
; CHECK-NEXT: Branch relaxation pass
; CHECK-NEXT: RISC-V Make Compressible
; CHECK-NEXT: Contiguously Lay Out Funclets
@@ -73,7 +74,6 @@
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: Stack Frame Layout Analysis
-; CHECK-NEXT: RISC-V Indirect Branch Tracking
; CHECK-NEXT: RISC-V pseudo instruction expansion pass
; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass
; CHECK-NEXT: Unpack machine instruction bundles
diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
index 19de864422bc5..c7f70a9d266c2 100644
--- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
@@ -195,6 +195,7 @@
; CHECK-NEXT: Implement the 'patchable-function' attribute
; CHECK-NEXT: Machine Copy Propagation Pass
; CHECK-NEXT: RISC-V Late Branch Optimisation Pass
+; CHECK-NEXT: RISC-V Indirect Branch Tracking
; CHECK-NEXT: Branch relaxation pass
; CHECK-NEXT: RISC-V Make Compressible
; CHECK-NEXT: Contiguously Lay Out Funclets
@@ -210,7 +211,6 @@
; CHECK-NEXT: Stack Frame Layout Analysis
; CHECK-NEXT: RISC-V Zcmp move merging pass
; CHECK-NEXT: RISC-V Zcmp Push/Pop optimization pass
-; CHECK-NEXT: RISC-V Indirect Branch Tracking
; CHECK-NEXT: RISC-V pseudo instruction expansion pass
; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass
; CHECK-NEXT: Unpack machine instruction bundles
>From be3cebdafc95bc90574a0d65c067e975baccae84 Mon Sep 17 00:00:00 2001
From: Jesse Huang <jesse.huang at sifive.com>
Date: Thu, 15 May 2025 01:11:37 -0700
Subject: [PATCH 2/3] fixup! Add comment
---
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 28283c9fd5b6d..c048243db4982 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -570,6 +570,9 @@ void RISCVPassConfig::addPreEmitPass() {
addPass(createMachineCopyPropagationPass(true));
if (TM->getOptLevel() >= CodeGenOptLevel::Default)
addPass(createRISCVLateBranchOptPass());
+ // The IndirectBranchTrackingPass inserts lpad and could have changed the
+ // basic block alignment. It must be done before Branch Relaxation to
+ // prevent the adjusted offset exceeding the branch range.
addPass(createRISCVIndirectBranchTrackingPass());
addPass(&BranchRelaxationPassID);
addPass(createRISCVMakeCompressibleOptPass());
>From 04de854a6d253d81fc6ab89d3e181a8a0fed42b9 Mon Sep 17 00:00:00 2001
From: Jesse Huang <jesse.huang at sifive.com>
Date: Sun, 25 May 2025 04:25:32 -0700
Subject: [PATCH 3/3] [RISCV] Make RISCVIndirectBranchTracking visible in debug
output
---
.../RISCV/RISCVIndirectBranchTracking.cpp | 19 ++++++++++++-------
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 1 +
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp b/llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
index 4660a975b20ae..da89589bee47a 100644
--- a/llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
+++ b/llvm/lib/Target/RISCV/RISCVIndirectBranchTracking.cpp
@@ -20,6 +20,9 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
+#define DEBUG_TYPE "riscv-indrect-branch-tracking"
+#define PASS_NAME "RISC-V Indirect Branch Tracking"
+
using namespace llvm;
cl::opt<uint32_t> PreferredLandingPadLabel(
@@ -27,27 +30,29 @@ cl::opt<uint32_t> PreferredLandingPadLabel(
cl::desc("Use preferred fixed label for all labels"));
namespace {
-class RISCVIndirectBranchTrackingPass : public MachineFunctionPass {
+class RISCVIndirectBranchTracking : public MachineFunctionPass {
public:
- RISCVIndirectBranchTrackingPass() : MachineFunctionPass(ID) {}
+ static char ID;
+ RISCVIndirectBranchTracking() : MachineFunctionPass(ID) {}
StringRef getPassName() const override {
- return "RISC-V Indirect Branch Tracking";
+ return PASS_NAME;
}
bool runOnMachineFunction(MachineFunction &MF) override;
private:
- static char ID;
const Align LpadAlign = Align(4);
};
} // end anonymous namespace
-char RISCVIndirectBranchTrackingPass::ID = 0;
+INITIALIZE_PASS(RISCVIndirectBranchTracking, DEBUG_TYPE, PASS_NAME, false, false)
+
+char RISCVIndirectBranchTracking::ID = 0;
FunctionPass *llvm::createRISCVIndirectBranchTrackingPass() {
- return new RISCVIndirectBranchTrackingPass();
+ return new RISCVIndirectBranchTracking();
}
static void emitLpad(MachineBasicBlock &MBB, const RISCVInstrInfo *TII,
@@ -57,7 +62,7 @@ static void emitLpad(MachineBasicBlock &MBB, const RISCVInstrInfo *TII,
.addImm(Label);
}
-bool RISCVIndirectBranchTrackingPass::runOnMachineFunction(
+bool RISCVIndirectBranchTracking::runOnMachineFunction(
MachineFunction &MF) {
const auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
const RISCVInstrInfo *TII = Subtarget.getInstrInfo();
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index c048243db4982..0407dfb768d36 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -146,6 +146,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
initializeRISCVDAGToDAGISelLegacyPass(*PR);
initializeRISCVMoveMergePass(*PR);
initializeRISCVPushPopOptPass(*PR);
+ initializeRISCVIndirectBranchTrackingPass(*PR);
initializeRISCVLoadStoreOptPass(*PR);
initializeRISCVExpandAtomicPseudoPass(*PR);
initializeRISCVRedundantCopyEliminationPass(*PR);
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