[llvm] 068868d - ELFObjectWriter: Replace Ctx.reportError with reportError
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Sat May 24 21:11:22 PDT 2025
Author: Fangrui Song
Date: 2025-05-24T21:11:17-07:00
New Revision: 068868d7ac71226ffb75ffbc194e97b6e5aa7bbf
URL: https://github.com/llvm/llvm-project/commit/068868d7ac71226ffb75ffbc194e97b6e5aa7bbf
DIFF: https://github.com/llvm/llvm-project/commit/068868d7ac71226ffb75ffbc194e97b6e5aa7bbf.diff
LOG: ELFObjectWriter: Replace Ctx.reportError with reportError
Prepare for removing MCContext from getRelocType functions.
Added:
Modified:
llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
llvm/lib/Target/CSKY/MCTargetDesc/CSKYELFObjectWriter.cpp
llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
llvm/lib/Target/VE/MCTargetDesc/VEELFObjectWriter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
index b8b2637354b1a..a3b7c530c3909 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
@@ -40,6 +40,9 @@ class AArch64ELFObjectWriter : public MCELFObjectTargetWriter {
const MCFixup &Fixup, bool IsPCRel) const override;
bool needsRelocateWithSymbol(const MCValue &Val, const MCSymbol &Sym,
unsigned Type) const override;
+ bool isNonILP32reloc(const MCFixup &Fixup, AArch64MCExpr::Specifier RefKind,
+ MCContext &Ctx) const;
+
bool IsILP32;
};
@@ -54,8 +57,9 @@ AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
IsILP32 ? ELF::R_AARCH64_P32_##rtype : ELF::R_AARCH64_##rtype
// assumes IsILP32 is true
-static bool isNonILP32reloc(const MCFixup &Fixup,
- AArch64MCExpr::Specifier RefKind, MCContext &Ctx) {
+bool AArch64ELFObjectWriter::isNonILP32reloc(const MCFixup &Fixup,
+ AArch64MCExpr::Specifier RefKind,
+ MCContext &Ctx) const {
if (Fixup.getTargetKind() != AArch64::fixup_aarch64_movw)
return false;
switch (RefKind) {
@@ -71,8 +75,8 @@ static bool isNonILP32reloc(const MCFixup &Fixup,
case AArch64MCExpr::VK_TPREL_G1_NC:
case AArch64MCExpr::VK_GOTTPREL_G1:
case AArch64MCExpr::VK_GOTTPREL_G0_NC:
- Ctx.reportError(Fixup.getLoc(),
- "absolute MOV relocation is not supported in ILP32");
+ reportError(Fixup.getLoc(),
+ "absolute MOV relocation is not supported in ILP32");
return true;
default:
return false;
@@ -111,7 +115,7 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
if (IsPCRel) {
switch (Kind) {
case FK_Data_1:
- Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
+ reportError(Fixup.getLoc(), "1-byte data relocations not supported");
return ELF::R_AARCH64_NONE;
case FK_Data_2:
return R_CLS(PREL16);
@@ -123,32 +127,31 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
}
case FK_Data_8:
if (IsILP32) {
- Ctx.reportError(Fixup.getLoc(), "8 byte PC relative data "
- "relocation is not supported in ILP32");
+ reportError(Fixup.getLoc(), "8 byte PC relative data "
+ "relocation is not supported in ILP32");
return ELF::R_AARCH64_NONE;
}
return ELF::R_AARCH64_PREL64;
case AArch64::fixup_aarch64_pcrel_adr_imm21:
if (SymLoc == AArch64MCExpr::VK_GOT_AUTH) {
if (IsILP32) {
- Ctx.reportError(Fixup.getLoc(),
- "ADR AUTH relocation is not supported in ILP32");
+ reportError(Fixup.getLoc(),
+ "ADR AUTH relocation is not supported in ILP32");
return ELF::R_AARCH64_NONE;
}
return ELF::R_AARCH64_AUTH_GOT_ADR_PREL_LO21;
}
if (SymLoc != AArch64MCExpr::VK_ABS)
- Ctx.reportError(Fixup.getLoc(),
- "invalid symbol kind for ADR relocation");
+ reportError(Fixup.getLoc(), "invalid symbol kind for ADR relocation");
return R_CLS(ADR_PREL_LO21);
case AArch64::fixup_aarch64_pcrel_adrp_imm21:
if (SymLoc == AArch64MCExpr::VK_ABS && !IsNC)
return R_CLS(ADR_PREL_PG_HI21);
if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) {
if (IsILP32) {
- Ctx.reportError(Fixup.getLoc(),
- "invalid fixup for 32-bit pcrel ADRP instruction "
- "VK_ABS VK_NC");
+ reportError(Fixup.getLoc(),
+ "invalid fixup for 32-bit pcrel ADRP instruction "
+ "VK_ABS VK_NC");
return ELF::R_AARCH64_NONE;
}
return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC;
@@ -157,8 +160,8 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
return R_CLS(ADR_GOT_PAGE);
if (SymLoc == AArch64MCExpr::VK_GOT_AUTH && !IsNC) {
if (IsILP32) {
- Ctx.reportError(Fixup.getLoc(),
- "ADRP AUTH relocation is not supported in ILP32");
+ reportError(Fixup.getLoc(),
+ "ADRP AUTH relocation is not supported in ILP32");
return ELF::R_AARCH64_NONE;
}
return ELF::R_AARCH64_AUTH_ADR_GOT_PAGE;
@@ -169,14 +172,13 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
return R_CLS(TLSDESC_ADR_PAGE21);
if (SymLoc == AArch64MCExpr::VK_TLSDESC_AUTH && !IsNC) {
if (IsILP32) {
- Ctx.reportError(Fixup.getLoc(),
- "ADRP AUTH relocation is not supported in ILP32");
+ reportError(Fixup.getLoc(),
+ "ADRP AUTH relocation is not supported in ILP32");
return ELF::R_AARCH64_NONE;
}
return ELF::R_AARCH64_AUTH_TLSDESC_ADR_PAGE21;
}
- Ctx.reportError(Fixup.getLoc(),
- "invalid symbol kind for ADRP relocation");
+ reportError(Fixup.getLoc(), "invalid symbol kind for ADRP relocation");
return ELF::R_AARCH64_NONE;
case AArch64::fixup_aarch64_pcrel_branch26:
return R_CLS(JUMP26);
@@ -189,8 +191,8 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
return R_CLS(GOT_LD_PREL19);
if (SymLoc == AArch64MCExpr::VK_GOT_AUTH) {
if (IsILP32) {
- Ctx.reportError(Fixup.getLoc(),
- "LDR AUTH relocation is not supported in ILP32");
+ reportError(Fixup.getLoc(),
+ "LDR AUTH relocation is not supported in ILP32");
return ELF::R_AARCH64_NONE;
}
return ELF::R_AARCH64_AUTH_GOT_LD_PREL19;
@@ -199,18 +201,18 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
case AArch64::fixup_aarch64_pcrel_branch14:
return R_CLS(TSTBR14);
case AArch64::fixup_aarch64_pcrel_branch16:
- Ctx.reportError(Fixup.getLoc(),
- "relocation of PAC/AUT instructions is not supported");
+ reportError(Fixup.getLoc(),
+ "relocation of PAC/AUT instructions is not supported");
return ELF::R_AARCH64_NONE;
case AArch64::fixup_aarch64_pcrel_branch9:
- Ctx.reportError(
+ reportError(
Fixup.getLoc(),
"relocation of compare-and-branch instructions not supported");
return ELF::R_AARCH64_NONE;
case AArch64::fixup_aarch64_pcrel_branch19:
return R_CLS(CONDBR19);
default:
- Ctx.reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
+ reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
return ELF::R_AARCH64_NONE;
}
} else {
@@ -218,7 +220,7 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
return ELF::R_AARCH64_NONE;
switch (Fixup.getTargetKind()) {
case FK_Data_1:
- Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
+ reportError(Fixup.getLoc(), "1-byte data relocations not supported");
return ELF::R_AARCH64_NONE;
case FK_Data_2:
return R_CLS(ABS16);
@@ -229,7 +231,7 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
: R_CLS(ABS32);
case FK_Data_8: {
if (IsILP32) {
- Ctx.reportError(
+ reportError(
Fixup.getLoc(),
"8 byte absolute data relocation is not supported in ILP32");
return ELF::R_AARCH64_NONE;
@@ -256,16 +258,16 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
return R_CLS(TLSDESC_ADD_LO12);
if (RefKind == AArch64MCExpr::VK_TLSDESC_AUTH_LO12) {
if (IsILP32) {
- Ctx.reportError(Fixup.getLoc(),
- "ADD AUTH relocation is not supported in ILP32");
+ reportError(Fixup.getLoc(),
+ "ADD AUTH relocation is not supported in ILP32");
return ELF::R_AARCH64_NONE;
}
return ELF::R_AARCH64_AUTH_TLSDESC_ADD_LO12;
}
if (RefKind == AArch64MCExpr::VK_GOT_AUTH_LO12 && IsNC) {
if (IsILP32) {
- Ctx.reportError(Fixup.getLoc(),
- "ADD AUTH relocation is not supported in ILP32");
+ reportError(Fixup.getLoc(),
+ "ADD AUTH relocation is not supported in ILP32");
return ELF::R_AARCH64_NONE;
}
return ELF::R_AARCH64_AUTH_GOT_ADD_LO12_NC;
@@ -273,8 +275,7 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
return R_CLS(ADD_ABS_LO12_NC);
- Ctx.reportError(Fixup.getLoc(),
- "invalid fixup for add (uimm12) instruction");
+ reportError(Fixup.getLoc(), "invalid fixup for add (uimm12) instruction");
return ELF::R_AARCH64_NONE;
case AArch64::fixup_aarch64_ldst_imm12_scale1:
if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
@@ -288,8 +289,8 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
return R_CLS(TLSLE_LDST8_TPREL_LO12_NC);
- Ctx.reportError(Fixup.getLoc(),
- "invalid fixup for 8-bit load/store instruction");
+ reportError(Fixup.getLoc(),
+ "invalid fixup for 8-bit load/store instruction");
return ELF::R_AARCH64_NONE;
case AArch64::fixup_aarch64_ldst_imm12_scale2:
if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
@@ -303,8 +304,8 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
return R_CLS(TLSLE_LDST16_TPREL_LO12_NC);
- Ctx.reportError(Fixup.getLoc(),
- "invalid fixup for 16-bit load/store instruction");
+ reportError(Fixup.getLoc(),
+ "invalid fixup for 16-bit load/store instruction");
return ELF::R_AARCH64_NONE;
case AArch64::fixup_aarch64_ldst_imm12_scale4:
if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
@@ -320,13 +321,13 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {
if (IsILP32)
return ELF::R_AARCH64_P32_LD32_GOT_LO12_NC;
- Ctx.reportError(Fixup.getLoc(), "4 byte unchecked GOT load/store "
- "relocation is not supported in LP64");
+ reportError(Fixup.getLoc(), "4 byte unchecked GOT load/store "
+ "relocation is not supported in LP64");
return ELF::R_AARCH64_NONE;
}
if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC) {
if (IsILP32) {
- Ctx.reportError(
+ reportError(
Fixup.getLoc(),
"4 byte checked GOT load/store relocation is not supported");
}
@@ -335,22 +336,22 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
if (IsILP32)
return ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC;
- Ctx.reportError(Fixup.getLoc(), "32-bit load/store "
- "relocation is not supported in LP64");
+ reportError(Fixup.getLoc(), "32-bit load/store "
+ "relocation is not supported in LP64");
return ELF::R_AARCH64_NONE;
}
if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC) {
if (IsILP32)
return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12;
- Ctx.reportError(
+ reportError(
Fixup.getLoc(),
"4 byte TLSDESC load/store relocation is not supported in LP64");
return ELF::R_AARCH64_NONE;
}
- Ctx.reportError(Fixup.getLoc(),
- "invalid fixup for 32-bit load/store instruction "
- "fixup_aarch64_ldst_imm12_scale4");
+ reportError(Fixup.getLoc(),
+ "invalid fixup for 32-bit load/store instruction "
+ "fixup_aarch64_ldst_imm12_scale4");
return ELF::R_AARCH64_NONE;
case AArch64::fixup_aarch64_ldst_imm12_scale8:
if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
@@ -367,9 +368,8 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
return (IsAuth ? ELF::R_AARCH64_AUTH_LD64_GOT_LO12_NC
: ELF::R_AARCH64_LD64_GOT_LO12_NC);
}
- Ctx.reportError(
- Fixup.getLoc(),
- "64-bit load/store relocation is not supported in ILP32");
+ reportError(Fixup.getLoc(),
+ "64-bit load/store relocation is not supported in ILP32");
return ELF::R_AARCH64_NONE;
}
if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
@@ -383,29 +383,27 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
if (!IsILP32)
return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
- Ctx.reportError(
- Fixup.getLoc(),
- "64-bit load/store relocation is not supported in ILP32");
+ reportError(Fixup.getLoc(),
+ "64-bit load/store relocation is not supported in ILP32");
return ELF::R_AARCH64_NONE;
}
if (SymLoc == AArch64MCExpr::VK_TLSDESC) {
if (!IsILP32)
return ELF::R_AARCH64_TLSDESC_LD64_LO12;
- Ctx.reportError(
- Fixup.getLoc(),
- "64-bit load/store relocation is not supported in ILP32");
+ reportError(Fixup.getLoc(),
+ "64-bit load/store relocation is not supported in ILP32");
return ELF::R_AARCH64_NONE;
}
if (SymLoc == AArch64MCExpr::VK_TLSDESC_AUTH) {
if (!IsILP32)
return ELF::R_AARCH64_AUTH_TLSDESC_LD64_LO12;
- Ctx.reportError(
+ reportError(
Fixup.getLoc(),
"64-bit load/store AUTH relocation is not supported in ILP32");
return ELF::R_AARCH64_NONE;
}
- Ctx.reportError(Fixup.getLoc(),
- "invalid fixup for 64-bit load/store instruction");
+ reportError(Fixup.getLoc(),
+ "invalid fixup for 64-bit load/store instruction");
return ELF::R_AARCH64_NONE;
case AArch64::fixup_aarch64_ldst_imm12_scale16:
if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
@@ -419,8 +417,8 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
return R_CLS(TLSLE_LDST128_TPREL_LO12_NC);
- Ctx.reportError(Fixup.getLoc(),
- "invalid fixup for 128-bit load/store instruction");
+ reportError(Fixup.getLoc(),
+ "invalid fixup for 128-bit load/store instruction");
return ELF::R_AARCH64_NONE;
// ILP32 case not reached here, tested with isNonILP32reloc
case AArch64::fixup_aarch64_movw:
@@ -482,11 +480,10 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1;
if (RefKind == AArch64MCExpr::VK_GOTTPREL_G0_NC)
return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC;
- Ctx.reportError(Fixup.getLoc(),
- "invalid fixup for movz/movk instruction");
+ reportError(Fixup.getLoc(), "invalid fixup for movz/movk instruction");
return ELF::R_AARCH64_NONE;
default:
- Ctx.reportError(Fixup.getLoc(), "Unknown ELF relocation type");
+ reportError(Fixup.getLoc(), "Unknown ELF relocation type");
return ELF::R_AARCH64_NONE;
}
}
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
index 40f8d83670a1c..516186e5684b4 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
@@ -84,8 +84,8 @@ unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx,
assert(SymA);
if (SymA->isUndefined()) {
- Ctx.reportError(Fixup.getLoc(),
- Twine("undefined label '") + SymA->getName() + "'");
+ reportError(Fixup.getLoc(),
+ Twine("undefined label '") + SymA->getName() + "'");
return ELF::R_AMDGPU_NONE;
}
return ELF::R_AMDGPU_REL16;
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
index 9fb681611594a..bf2e717aa20c8 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp
@@ -83,10 +83,10 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
uint8_t Specifier = Target.getSpecifier();
auto CheckFDPIC = [&](uint32_t Type) {
if (getOSABI() != ELF::ELFOSABI_ARM_FDPIC)
- Ctx.reportError(Fixup.getLoc(),
- "relocation " +
- object::getELFRelocationTypeName(ELF::EM_ARM, Type) +
- " only supported in FDPIC mode");
+ reportError(Fixup.getLoc(),
+ "relocation " +
+ object::getELFRelocationTypeName(ELF::EM_ARM, Type) +
+ " only supported in FDPIC mode");
return Type;
};
@@ -111,13 +111,13 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
if (IsPCRel) {
switch (Fixup.getTargetKind()) {
default:
- Ctx.reportError(Fixup.getLoc(), "unsupported relocation type");
+ reportError(Fixup.getLoc(), "unsupported relocation type");
return ELF::R_ARM_NONE;
case FK_Data_4:
switch (Specifier) {
default:
- Ctx.reportError(Fixup.getLoc(),
- "invalid fixup for 4-byte pc-relative data relocation");
+ reportError(Fixup.getLoc(),
+ "invalid fixup for 4-byte pc-relative data relocation");
return ELF::R_ARM_NONE;
case ARMMCExpr::VK_None: {
if (const auto *SA = Target.getAddSym()) {
@@ -203,13 +203,12 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
}
switch (Kind) {
default:
- Ctx.reportError(Fixup.getLoc(), "unsupported relocation type");
+ reportError(Fixup.getLoc(), "unsupported relocation type");
return ELF::R_ARM_NONE;
case FK_Data_1:
switch (Specifier) {
default:
- Ctx.reportError(Fixup.getLoc(),
- "invalid fixup for 1-byte data relocation");
+ reportError(Fixup.getLoc(), "invalid fixup for 1-byte data relocation");
return ELF::R_ARM_NONE;
case ARMMCExpr::VK_None:
return ELF::R_ARM_ABS8;
@@ -217,8 +216,7 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
case FK_Data_2:
switch (Specifier) {
default:
- Ctx.reportError(Fixup.getLoc(),
- "invalid fixup for 2-byte data relocation");
+ reportError(Fixup.getLoc(), "invalid fixup for 2-byte data relocation");
return ELF::R_ARM_NONE;
case ARMMCExpr::VK_None:
return ELF::R_ARM_ABS16;
@@ -226,8 +224,7 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
case FK_Data_4:
switch (Specifier) {
default:
- Ctx.reportError(Fixup.getLoc(),
- "invalid fixup for 4-byte data relocation");
+ reportError(Fixup.getLoc(), "invalid fixup for 4-byte data relocation");
return ELF::R_ARM_NONE;
case ARMMCExpr::VK_ARM_NONE:
return ELF::R_ARM_NONE;
@@ -282,7 +279,7 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
case ARM::fixup_arm_movt_hi16:
switch (Specifier) {
default:
- Ctx.reportError(Fixup.getLoc(), "invalid fixup for ARM MOVT instruction");
+ reportError(Fixup.getLoc(), "invalid fixup for ARM MOVT instruction");
return ELF::R_ARM_NONE;
case ARMMCExpr::VK_None:
return ELF::R_ARM_MOVT_ABS;
@@ -292,7 +289,7 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
case ARM::fixup_arm_movw_lo16:
switch (Specifier) {
default:
- Ctx.reportError(Fixup.getLoc(), "invalid fixup for ARM MOVW instruction");
+ reportError(Fixup.getLoc(), "invalid fixup for ARM MOVW instruction");
return ELF::R_ARM_NONE;
case ARMMCExpr::VK_None:
return ELF::R_ARM_MOVW_ABS_NC;
@@ -302,8 +299,7 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
case ARM::fixup_t2_movt_hi16:
switch (Specifier) {
default:
- Ctx.reportError(Fixup.getLoc(),
- "invalid fixup for Thumb MOVT instruction");
+ reportError(Fixup.getLoc(), "invalid fixup for Thumb MOVT instruction");
return ELF::R_ARM_NONE;
case ARMMCExpr::VK_None:
return ELF::R_ARM_THM_MOVT_ABS;
@@ -313,8 +309,7 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
case ARM::fixup_t2_movw_lo16:
switch (Specifier) {
default:
- Ctx.reportError(Fixup.getLoc(),
- "invalid fixup for Thumb MOVW instruction");
+ reportError(Fixup.getLoc(), "invalid fixup for Thumb MOVW instruction");
return ELF::R_ARM_NONE;
case ARMMCExpr::VK_None:
return ELF::R_ARM_THM_MOVW_ABS_NC;
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYELFObjectWriter.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYELFObjectWriter.cpp
index d424399ce6bc9..74149aeec78f1 100644
--- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYELFObjectWriter.cpp
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYELFObjectWriter.cpp
@@ -61,7 +61,7 @@ unsigned CSKYELFObjectWriter::getRelocType(MCContext &Ctx,
switch (Kind) {
default:
LLVM_DEBUG(dbgs() << "Unknown Kind1 = " << Kind);
- Ctx.reportError(Fixup.getLoc(), "Unsupported relocation type");
+ reportError(Fixup.getLoc(), "Unsupported relocation type");
return ELF::R_CKCORE_NONE;
case FK_Data_4:
case FK_PCRel_4:
@@ -86,13 +86,13 @@ unsigned CSKYELFObjectWriter::getRelocType(MCContext &Ctx,
switch (Kind) {
default:
LLVM_DEBUG(dbgs() << "Unknown Kind2 = " << Kind);
- Ctx.reportError(Fixup.getLoc(), "Unsupported relocation type");
+ reportError(Fixup.getLoc(), "Unsupported relocation type");
return ELF::R_CKCORE_NONE;
case FK_Data_1:
- Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
+ reportError(Fixup.getLoc(), "1-byte data relocations not supported");
return ELF::R_CKCORE_NONE;
case FK_Data_2:
- Ctx.reportError(Fixup.getLoc(), "2-byte data relocations not supported");
+ reportError(Fixup.getLoc(), "2-byte data relocations not supported");
return ELF::R_CKCORE_NONE;
case FK_Data_4:
if (Expr->getKind() == MCExpr::Target) {
@@ -121,12 +121,11 @@ unsigned CSKYELFObjectWriter::getRelocType(MCContext &Ctx,
return ELF::R_CKCORE_ADDR32;
LLVM_DEBUG(dbgs() << "Unknown FK_Data_4 TK = " << TK);
- Ctx.reportError(Fixup.getLoc(), "unknown target FK_Data_4");
+ reportError(Fixup.getLoc(), "unknown target FK_Data_4");
} else {
switch (Modifier) {
default:
- Ctx.reportError(Fixup.getLoc(),
- "invalid fixup for 4-byte data relocation");
+ reportError(Fixup.getLoc(), "invalid fixup for 4-byte data relocation");
return ELF::R_CKCORE_NONE;
case CSKYMCExpr::VK_GOT:
return ELF::R_CKCORE_GOT32;
@@ -146,7 +145,7 @@ unsigned CSKYELFObjectWriter::getRelocType(MCContext &Ctx,
}
return ELF::R_CKCORE_NONE;
case FK_Data_8:
- Ctx.reportError(Fixup.getLoc(), "8-byte data relocations not supported");
+ reportError(Fixup.getLoc(), "8-byte data relocations not supported");
return ELF::R_CKCORE_NONE;
case CSKY::fixup_csky_addr32:
return ELF::R_CKCORE_ADDR32;
diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp
index c6305d8693a26..e141670a71dd2 100644
--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp
+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchELFObjectWriter.cpp
@@ -76,13 +76,13 @@ unsigned LoongArchELFObjectWriter::getRelocType(MCContext &Ctx,
return Kind;
switch (Kind) {
default:
- Ctx.reportError(Fixup.getLoc(), "Unsupported relocation type");
+ reportError(Fixup.getLoc(), "Unsupported relocation type");
return ELF::R_LARCH_NONE;
case FK_Data_1:
- Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
+ reportError(Fixup.getLoc(), "1-byte data relocations not supported");
return ELF::R_LARCH_NONE;
case FK_Data_2:
- Ctx.reportError(Fixup.getLoc(), "2-byte data relocations not supported");
+ reportError(Fixup.getLoc(), "2-byte data relocations not supported");
return ELF::R_LARCH_NONE;
case FK_Data_4:
return IsPCRel ? ELF::R_LARCH_32_PCREL : ELF::R_LARCH_32;
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
index 9e2646a457b56..96826a51907c0 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
@@ -178,8 +178,7 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx,
case FK_NONE:
return ELF::R_MIPS_NONE;
case FK_Data_1:
- Ctx.reportError(Fixup.getLoc(),
- "MIPS does not support one byte relocations");
+ reportError(Fixup.getLoc(), "MIPS does not support one byte relocations");
return ELF::R_MIPS_NONE;
case Mips::fixup_Mips_16:
case FK_Data_2:
@@ -341,7 +340,7 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx,
return ELF::R_MICROMIPS_JALR;
}
- Ctx.reportError(Fixup.getLoc(), "unsupported relocation type");
+ reportError(Fixup.getLoc(), "unsupported relocation type");
return ELF::R_MIPS_NONE;
}
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
index d2db022ababc2..8d6f7a94b0519 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
@@ -105,7 +105,7 @@ unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
case PPC::fixup_ppc_br24_notoc:
switch (Spec) {
default:
- Ctx.reportError(Loc, "unsupported relocation type");
+ reportError(Loc, "unsupported relocation type");
break;
case PPCMCExpr::VK_None:
Type = ELF::R_PPC_REL24;
@@ -128,7 +128,7 @@ unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
case PPC::fixup_ppc_half16:
switch (Spec) {
default:
- Ctx.reportError(Loc, "unsupported relocation type");
+ reportError(Loc, "unsupported relocation type");
return ELF::R_PPC_NONE;
case PPCMCExpr::VK_None:
return ELF::R_PPC_REL16;
@@ -142,12 +142,12 @@ unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
break;
case PPC::fixup_ppc_half16ds:
case PPC::fixup_ppc_half16dq:
- Ctx.reportError(Loc, "unsupported relocation type");
+ reportError(Loc, "unsupported relocation type");
break;
case PPC::fixup_ppc_pcrel34:
switch (Spec) {
default:
- Ctx.reportError(Loc, "unsupported relocation type");
+ reportError(Loc, "unsupported relocation type");
break;
case PPCMCExpr::VK_PCREL:
Type = ELF::R_PPC64_PCREL34;
@@ -185,7 +185,7 @@ unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
case PPC::fixup_ppc_half16:
switch (Spec) {
default:
- Ctx.reportError(Loc, "unsupported relocation type");
+ reportError(Loc, "unsupported relocation type");
break;
case PPCMCExpr::VK_LO:
return ELF::R_PPC_ADDR16_LO;
@@ -361,7 +361,7 @@ unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
case PPC::fixup_ppc_half16dq:
switch (Spec) {
default:
- Ctx.reportError(Loc, "unsupported relocation type");
+ reportError(Loc, "unsupported relocation type");
break;
case PPCMCExpr::VK_LO:
return ELF::R_PPC64_ADDR16_LO_DS;
@@ -409,7 +409,7 @@ unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
case PPC::fixup_ppc_nofixup:
switch (Spec) {
default:
- Ctx.reportError(Loc, "unsupported relocation type");
+ reportError(Loc, "unsupported relocation type");
break;
case PPCMCExpr::VK_TLSGD:
if (is64Bit())
@@ -437,7 +437,7 @@ unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
case PPC::fixup_ppc_imm34:
switch (Spec) {
default:
- Ctx.reportError(Loc, "unsupported relocation type");
+ reportError(Loc, "unsupported relocation type");
break;
case PPCMCExpr::VK_DTPREL:
Type = ELF::R_PPC64_DTPREL34;
@@ -450,7 +450,7 @@ unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
case FK_Data_8:
switch (Spec) {
default:
- Ctx.reportError(Loc, "unsupported relocation type");
+ reportError(Loc, "unsupported relocation type");
break;
case PPCMCExpr::VK_TOCBASE:
Type = ELF::R_PPC64_TOC;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
index dd291cee32dc6..4cde08a41f41b 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
@@ -65,9 +65,8 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
case ELF::R_RISCV_GOT32_PCREL:
if (Kind == FK_Data_4)
break;
- Ctx.reportError(Fixup.getLoc(),
- "%" + RISCVMCExpr::getSpecifierName(Spec) +
- " can only be used in a .word directive");
+ reportError(Fixup.getLoc(), "%" + RISCVMCExpr::getSpecifierName(Spec) +
+ " can only be used in a .word directive");
return ELF::R_RISCV_NONE;
default:
break;
@@ -81,7 +80,7 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
if (IsPCRel) {
switch (Kind) {
default:
- Ctx.reportError(Fixup.getLoc(), "unsupported relocation type");
+ reportError(Fixup.getLoc(), "unsupported relocation type");
return ELF::R_RISCV_NONE;
case FK_Data_4:
return ELF::R_RISCV_32_PCREL;
@@ -112,14 +111,14 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
switch (Kind) {
default:
- Ctx.reportError(Fixup.getLoc(), "unsupported relocation type");
+ reportError(Fixup.getLoc(), "unsupported relocation type");
return ELF::R_RISCV_NONE;
case FK_Data_1:
- Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
+ reportError(Fixup.getLoc(), "1-byte data relocations not supported");
return ELF::R_RISCV_NONE;
case FK_Data_2:
- Ctx.reportError(Fixup.getLoc(), "2-byte data relocations not supported");
+ reportError(Fixup.getLoc(), "2-byte data relocations not supported");
return ELF::R_RISCV_NONE;
case FK_Data_4:
if (Expr->getKind() == MCExpr::Target) {
diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEELFObjectWriter.cpp b/llvm/lib/Target/VE/MCTargetDesc/VEELFObjectWriter.cpp
index 5d5b4c01c22e5..1b3e9784de3ba 100644
--- a/llvm/lib/Target/VE/MCTargetDesc/VEELFObjectWriter.cpp
+++ b/llvm/lib/Target/VE/MCTargetDesc/VEELFObjectWriter.cpp
@@ -59,23 +59,23 @@ unsigned VEELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
if (IsPCRel) {
switch (Fixup.getTargetKind()) {
default:
- Ctx.reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
+ reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
return ELF::R_VE_NONE;
case FK_Data_1:
case FK_PCRel_1:
- Ctx.reportError(Fixup.getLoc(),
- "1-byte pc-relative data relocation is not supported");
+ reportError(Fixup.getLoc(),
+ "1-byte pc-relative data relocation is not supported");
return ELF::R_VE_NONE;
case FK_Data_2:
- Ctx.reportError(Fixup.getLoc(),
- "2-byte pc-relative data relocation is not supported");
+ reportError(Fixup.getLoc(),
+ "2-byte pc-relative data relocation is not supported");
return ELF::R_VE_NONE;
case FK_Data_4:
return ELF::R_VE_SREL32;
case FK_Data_8:
case FK_PCRel_8:
- Ctx.reportError(Fixup.getLoc(),
- "8-byte pc-relative data relocation is not supported");
+ reportError(Fixup.getLoc(),
+ "8-byte pc-relative data relocation is not supported");
return ELF::R_VE_NONE;
case VE::fixup_ve_reflong:
case VE::fixup_ve_srel32:
@@ -89,13 +89,13 @@ unsigned VEELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
switch (Fixup.getTargetKind()) {
default:
- Ctx.reportError(Fixup.getLoc(), "Unknown ELF relocation type");
+ reportError(Fixup.getLoc(), "Unknown ELF relocation type");
return ELF::R_VE_NONE;
case FK_Data_1:
- Ctx.reportError(Fixup.getLoc(), "1-byte data relocation is not supported");
+ reportError(Fixup.getLoc(), "1-byte data relocation is not supported");
return ELF::R_VE_NONE;
case FK_Data_2:
- Ctx.reportError(Fixup.getLoc(), "2-byte data relocation is not supported");
+ reportError(Fixup.getLoc(), "2-byte data relocation is not supported");
return ELF::R_VE_NONE;
case FK_Data_4:
return ELF::R_VE_REFLONG;
@@ -104,20 +104,20 @@ unsigned VEELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
case VE::fixup_ve_reflong:
return ELF::R_VE_REFLONG;
case VE::fixup_ve_srel32:
- Ctx.reportError(Fixup.getLoc(),
- "A non pc-relative srel32 relocation is not supported");
+ reportError(Fixup.getLoc(),
+ "A non pc-relative srel32 relocation is not supported");
return ELF::R_VE_NONE;
case VE::fixup_ve_hi32:
return ELF::R_VE_HI32;
case VE::fixup_ve_lo32:
return ELF::R_VE_LO32;
case VE::fixup_ve_pc_hi32:
- Ctx.reportError(Fixup.getLoc(),
- "A non pc-relative pc_hi32 relocation is not supported");
+ reportError(Fixup.getLoc(),
+ "A non pc-relative pc_hi32 relocation is not supported");
return ELF::R_VE_NONE;
case VE::fixup_ve_pc_lo32:
- Ctx.reportError(Fixup.getLoc(),
- "A non pc-relative pc_lo32 relocation is not supported");
+ reportError(Fixup.getLoc(),
+ "A non pc-relative pc_lo32 relocation is not supported");
return ELF::R_VE_NONE;
case VE::fixup_ve_got_hi32:
return ELF::R_VE_GOT_HI32;
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