[llvm] a9b2998 - [VPlan] Skip cost assert if VPlan converted to single-scalar recipes.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Sat May 24 03:09:56 PDT 2025
Author: Florian Hahn
Date: 2025-05-24T11:09:27+01:00
New Revision: a9b2998e315af64b7a68606af9064db425699c39
URL: https://github.com/llvm/llvm-project/commit/a9b2998e315af64b7a68606af9064db425699c39
DIFF: https://github.com/llvm/llvm-project/commit/a9b2998e315af64b7a68606af9064db425699c39.diff
LOG: [VPlan] Skip cost assert if VPlan converted to single-scalar recipes.
Check if a VPlan transform converted recipes to single-scalar
VPReplicateRecipes (after 07c085af3efcd67503232f99a1652efc6e54c1a9). If
that's the case, the legacy cost model incorrectly overestimates the cost.
Fixes https://github.com/llvm/llvm-project/issues/141237.
Added:
Modified:
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
llvm/lib/Transforms/Vectorize/VPlanHelpers.h
llvm/test/Transforms/LoopVectorize/X86/uniform_load.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 275b3d5678560..8a35afbb73f3c 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -7082,6 +7082,11 @@ InstructionCost VPCostContext::getLegacyCost(Instruction *UI,
return CM.getInstructionCost(UI, VF);
}
+bool VPCostContext::isLegacyUniformAfterVectorization(Instruction *I,
+ ElementCount VF) const {
+ return CM.isUniformAfterVectorization(I, VF);
+}
+
bool VPCostContext::skipCostComputation(Instruction *UI, bool IsVector) const {
return CM.ValuesToIgnore.contains(UI) ||
(IsVector && CM.VecValuesToIgnore.contains(UI)) ||
@@ -7315,7 +7320,8 @@ InstructionCost LoopVectorizationPlanner::cost(VPlan &Plan,
/// cost-model did not account for.
static bool planContainsAdditionalSimplifications(VPlan &Plan,
VPCostContext &CostCtx,
- Loop *TheLoop) {
+ Loop *TheLoop,
+ ElementCount VF) {
// First collect all instructions for the recipes in Plan.
auto GetInstructionForCost = [](const VPRecipeBase *R) -> Instruction * {
if (auto *S = dyn_cast<VPSingleDefRecipe>(R))
@@ -7352,6 +7358,16 @@ static bool planContainsAdditionalSimplifications(VPlan &Plan,
// comparing against the legacy cost isn't desirable.
if (isa<VPPartialReductionRecipe>(&R))
return true;
+
+ /// If a VPlan transform folded a recipe to one producing a single-scalar,
+ /// but the original instruction wasn't uniform-after-vectorization in the
+ /// legacy cost model, the legacy cost overestimates the actual cost.
+ if (auto *RepR = dyn_cast<VPReplicateRecipe>(&R)) {
+ if (RepR->isSingleScalar() &&
+ !CostCtx.isLegacyUniformAfterVectorization(
+ RepR->getUnderlyingInstr(), VF))
+ return true;
+ }
if (Instruction *UI = GetInstructionForCost(&R)) {
// If we adjusted the predicate of the recipe, the cost in the legacy
// cost model may be
diff erent.
@@ -7477,9 +7493,10 @@ VectorizationFactor LoopVectorizationPlanner::computeBestVF() {
// legacy cost model doesn't properly model costs for such loops.
assert((BestFactor.Width == LegacyVF.Width || BestPlan.hasEarlyExit() ||
planContainsAdditionalSimplifications(getPlanFor(BestFactor.Width),
- CostCtx, OrigLoop) ||
- planContainsAdditionalSimplifications(getPlanFor(LegacyVF.Width),
- CostCtx, OrigLoop)) &&
+ CostCtx, OrigLoop,
+ BestFactor.Width) ||
+ planContainsAdditionalSimplifications(
+ getPlanFor(LegacyVF.Width), CostCtx, OrigLoop, LegacyVF.Width)) &&
" VPlan cost model and legacy cost model disagreed");
assert((BestFactor.Width.isScalar() || BestFactor.ScalarCost > 0) &&
"when vectorizing, the scalar cost must be computed.");
diff --git a/llvm/lib/Transforms/Vectorize/VPlanHelpers.h b/llvm/lib/Transforms/Vectorize/VPlanHelpers.h
index 1d42c8f5f3737..0446991ebfff3 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanHelpers.h
+++ b/llvm/lib/Transforms/Vectorize/VPlanHelpers.h
@@ -364,6 +364,11 @@ struct VPCostContext {
/// Returns the OperandInfo for \p V, if it is a live-in.
TargetTransformInfo::OperandValueInfo getOperandInfo(VPValue *V) const;
+
+ /// Return true if \p I is considered uniform-after-vectorization in the
+ /// legacy cost model for \p VF. Only used to check for additional VPlan
+ /// simplifications.
+ bool isLegacyUniformAfterVectorization(Instruction *I, ElementCount VF) const;
};
/// This class can be used to assign names to VPValues. For VPValues without
diff --git a/llvm/test/Transforms/LoopVectorize/X86/uniform_load.ll b/llvm/test/Transforms/LoopVectorize/X86/uniform_load.ll
index 7b2e65d1b02e3..a9a1f5c9b3d0a 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/uniform_load.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/uniform_load.ll
@@ -1,4 +1,10 @@
-; RUN: opt -passes=loop-vectorize -S -mcpu=core-avx2 < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "middle.block:" --version 5
+; RUN: opt -passes=loop-vectorize -S %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+ at inc = global float 5.000000e-01, align 4
;float inc = 0.5;
;void foo(ptr A, unsigned N) {
@@ -8,40 +14,116 @@
; }
;}
-; CHECK-LABEL: foo
-; CHECK: vector.body
-; CHECK: load <8 x float>
-; CHECK: fadd <8 x float>
-; CHECK: store <8 x float>
+define void @foo(ptr nocapture noalias %A, i64 %N) #0 {
+; CHECK-LABEL: define void @foo(
+; CHECK-SAME: ptr noalias captures(none) [[A:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br i1 false, [[SCALAR_PH:label %.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr @inc, align 4
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x float> poison, float [[TMP1]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x float> [[BROADCAST_SPLATINSERT]], <8 x float> poison, <8 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds float, ptr [[A]], i64 0
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 8
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 16
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 24
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x float>, ptr [[TMP3]], align 4
+; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x float>, ptr [[TMP4]], align 4
+; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x float>, ptr [[TMP5]], align 4
+; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x float>, ptr [[TMP6]], align 4
+; CHECK-NEXT: [[TMP7:%.*]] = fadd <8 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP8:%.*]] = fadd <8 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD2]]
+; CHECK-NEXT: [[TMP9:%.*]] = fadd <8 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD3]]
+; CHECK-NEXT: [[TMP10:%.*]] = fadd <8 x float> [[BROADCAST_SPLAT]], [[WIDE_LOAD4]]
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 8
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 16
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 24
+; CHECK-NEXT: store <8 x float> [[TMP7]], ptr [[TMP14]], align 4
+; CHECK-NEXT: store <8 x float> [[TMP8]], ptr [[TMP11]], align 4
+; CHECK-NEXT: store <8 x float> [[TMP9]], ptr [[TMP12]], align 4
+; CHECK-NEXT: store <8 x float> [[TMP10]], ptr [[TMP13]], align 4
+; CHECK-NEXT: br label %[[MIDDLE_BLOCK:.*]]
+; CHECK: [[MIDDLE_BLOCK]]:
+;
+entry:
+ br label %loop
-target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
-target triple = "x86_64-unknown-linux-gnu"
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %l.inc = load float, ptr @inc, align 4
+ %gep.A = getelementptr inbounds float, ptr %A, i64 %iv
+ %l.A = load float, ptr %gep.A, align 4
+ %add = fadd float %l.inc, %l.A
+ store float %add, ptr %gep.A, align 4
+ %iv.next = add nuw nsw i64 %iv, 1
+ %ec = icmp eq i64 %iv.next, 32
+ br i1 %ec, label %exit, label %loop
- at inc = global float 5.000000e-01, align 4
+exit:
+ ret void
+}
-define void @foo(ptr nocapture %A, i32 %N) #0 {
+define void @uniform_load_can_fold_users(ptr noalias %src, ptr %dst, i64 %start, double %d) {
+; CHECK-LABEL: define void @uniform_load_can_fold_users(
+; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr [[DST:%.*]], i64 [[START:%.*]], double [[D:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[START]], 1
+; CHECK-NEXT: [[SMIN:%.*]] = call i64 @llvm.smin.i64(i64 [[START]], i64 0)
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[SMIN]]
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 2
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], [[SCALAR_PH:label %.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 2
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF]]
+; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[START]], [[N_VEC]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 0
+; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 1
+; CHECK-NEXT: [[TMP5:%.*]] = load double, ptr [[SRC]], align 8
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x double> poison, double [[TMP5]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x double> [[BROADCAST_SPLATINSERT]], <2 x double> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP6:%.*]] = fmul <2 x double> [[BROADCAST_SPLAT]], splat (double 9.000000e+00)
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP6]], i32 0
+; CHECK-NEXT: [[TMP8:%.*]] = fdiv double [[TMP7]], [[D]]
+; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[TMP3]], 1
+; CHECK-NEXT: [[TMP10:%.*]] = sub i64 [[TMP4]], 1
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr double, ptr [[DST]], i64 [[TMP3]]
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr double, ptr [[DST]], i64 [[TMP4]]
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr double, ptr [[TMP11]], i64 [[TMP9]]
+; CHECK-NEXT: [[TMP14:%.*]] = getelementptr double, ptr [[TMP12]], i64 [[TMP10]]
+; CHECK-NEXT: store double [[TMP8]], ptr [[TMP13]], align 8
+; CHECK-NEXT: store double [[TMP8]], ptr [[TMP14]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
+; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+;
entry:
- %cmp3 = icmp eq i32 %N, 0
- br i1 %cmp3, label %for.end, label %for.body.preheader
-
-for.body.preheader: ; preds = %entry
- br label %for.body
-
-for.body: ; preds = %for.body.preheader, %for.body
- %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ]
- %0 = load float, ptr @inc, align 4
- %arrayidx = getelementptr inbounds float, ptr %A, i64 %indvars.iv
- %1 = load float, ptr %arrayidx, align 4
- %add = fadd float %0, %1
- store float %add, ptr %arrayidx, align 4
- %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
- %lftr.wideiv = trunc i64 %indvars.iv.next to i32
- %exitcond = icmp eq i32 %lftr.wideiv, %N
- br i1 %exitcond, label %for.end.loopexit, label %for.body
-
-for.end.loopexit: ; preds = %for.body
- br label %for.end
-
-for.end: ; preds = %for.end.loopexit, %entry
+ br label %loop
+
+loop:
+ %iv.1 = phi i64 [ 0, %entry ], [ %iv.1.next, %loop ]
+ %iv.2 = phi i64 [ %start, %entry ], [ %iv.2.next, %loop ]
+ %l = load double, ptr %src, align 8
+ %m = fmul double %l, 9.0
+ %div = fdiv double %m, %d
+ %sub = sub i64 %iv.1, 1
+ %gep.1 = getelementptr double, ptr %dst, i64 %iv.1
+ %gep.2 = getelementptr double, ptr %gep.1, i64 %sub
+ store double %div, ptr %gep.2, align 8
+ %iv.1.next = add i64 %iv.1, 1
+ %iv.2.next = add i64 %iv.2, -1
+ %ec = icmp sgt i64 %iv.2, 0
+ br i1 %ec , label %loop, label %exit
+
+exit:
ret void
}
+
+attributes #0 = { "target-cpu"="core-avx2" }
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