[llvm] [NVPTX] Add pm_event intrinsics (PR #141278)

[Alex MacLean via llvm-commits]

================
@@ -1868,6 +1868,38 @@ If the request failed, the behavior of these intrinsics is undefined.
 
 For more information, refer `PTX ISA <https://docs.nvidia.com/cuda/parallel-thread-execution/?a#parallel-synchronization-and-communication-instructions-clusterlaunchcontrol-query-cancel>`__.
 
+Perf Monitor Event Intrinsics
+-----------------------------
+
+'``llvm.nvvm.pm.event.[idx|mask]``' Intrinsics
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+
+.. code-block:: llvm
+
+    declare void @llvm.nvvm.pm.event.idx(i32 immarg %idx_val)
----------------
AlexMaclean wrote:

Perhaps we should just expose the "mask" variant in the IR? It should be trivial to lower to the non-mask variant during ISel for cases when there is only one bit set in the mask. These are similar enough that it might make sense to just have a single flexible canonical form.

https://github.com/llvm/llvm-project/pull/141278