[llvm] 75d62ee - [RISCV] Correctly account for the copy cost of GPR pairs in RISCVMakeCompressible. (#141251)

[via llvm-commits]

Author: Craig Topper
Date: 2025-05-23T11:37:42-07:00
New Revision: 75d62ee853a387f02b9dcf6a22070341974ffb89

URL: https://github.com/llvm/llvm-project/commit/75d62ee853a387f02b9dcf6a22070341974ffb89
DIFF: https://github.com/llvm/llvm-project/commit/75d62ee853a387f02b9dcf6a22070341974ffb89.diff

LOG: [RISCV] Correctly account for the copy cost of GPR pairs in RISCVMakeCompressible. (#141251)

GPR pairs require 2 ADDIs to copy, so we need to be updating more
instructions to get a benefit.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
    llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
index 7ed2e67635517..3621b7dc73312 100644
--- a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
@@ -332,9 +332,11 @@ static Register analyzeCompressibleUses(MachineInstr &FirstMI,
   // are required for a code size reduction. If no base adjustment is required,
   // then copying the register costs one new c.mv (or c.li Rd, 0 for "copying"
   // the zero register) and therefore two uses are required for a code size
-  // reduction.
-  if (MIs.size() < 2 || (RegImm.Imm != 0 && MIs.size() < 3))
-    return RISCV::NoRegister;
+  // reduction. For GPR pairs, we need 2 ADDIs to copy so we need three users.
+  unsigned CopyCost = RISCV::GPRPairRegClass.contains(RegImm.Reg) ? 2 : 1;
+  assert((RegImm.Imm == 0 || CopyCost == 1) && "GPRPair should have zero imm");
+  if (MIs.size() <= CopyCost || (RegImm.Imm != 0 && MIs.size() <= 2))
+    return Register();
 
   // Find a compressible register which will be available from the first
   // instruction we care about to the last.

diff  --git a/llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir b/llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir
index 48f489458f93b..e9a5fe0b18a7a 100644
--- a/llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir
+++ b/llvm/test/CodeGen/RISCV/make-compressible-zilsd.mir
@@ -70,6 +70,13 @@
     ret void
   }
 
+  define void @store_common_value_double_no_opt2(ptr %a, i32 %b, double %c, double %d, double %e) #0 {
+  entry:
+    store volatile double %e, ptr %a, align 8
+    store volatile double %e, ptr %a, align 8
+    ret void
+  }
+
   define void @store_common_ptr_double_no_opt(double %a, i32 %b, i32 %c, i32 %d, i32 %e, ptr %p) #0 {
   entry:
     store volatile double %a, ptr %p, align 8
@@ -246,6 +253,24 @@ body:             |
     SD_RV32 killed renamable $x16_x17, killed renamable $x10, 0 :: (store (s64) into %ir.a)
     PseudoRET
 
+...
+---
+name:            store_common_value_double_no_opt2
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x16, $x17
+
+    ; RV32-LABEL: name: store_common_value_double_no_opt2
+    ; RV32: liveins: $x10, $x16, $x17
+    ; RV32-NEXT: {{  $}}
+    ; RV32-NEXT: SD_RV32 renamable $x16_x17, renamable $x10, 0 :: (volatile store (s64) into %ir.a)
+    ; RV32-NEXT: SD_RV32 killed renamable $x16_x17, killed renamable $x10, 0 :: (volatile store (s64) into %ir.a)
+    ; RV32-NEXT: PseudoRET
+    SD_RV32 renamable $x16_x17, renamable $x10, 0 :: (volatile store (s64) into %ir.a)
+    SD_RV32 killed renamable $x16_x17, killed renamable $x10, 0 :: (volatile store (s64) into %ir.a)
+    PseudoRET
+
 ...
 ---
 name:            store_common_ptr_double_no_opt