[llvm] [AArch64][SelectionDAG] Add type legalization for partial reduce wide adds (PR #141075)

[Philip Reames via llvm-commits]

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@@ -12644,6 +12644,8 @@ SDValue DAGCombiner::foldPartialReduceMLAMulOp(SDNode *N) {
           TLI.getTypeToTransformTo(*Context, LHSExtOpVT)))
     return SDValue();
 
+  EVT ResultVT = N->getValueType(0);
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preames wrote:

The extraction of ResultVT appears to be a separable NFC.  Please separate and land, and then rebase.

https://github.com/llvm/llvm-project/pull/141075