[llvm] [RISCV][TTI] Implement getPartialReductionCost for the vqdotq cases (PR #140974)

[Luke Lau via llvm-commits]

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@@ -294,6 +294,29 @@ RISCVTTIImpl::getPopcntSupport(unsigned TyWidth) const {
              : TTI::PSK_Software;
 }
 
+InstructionCost RISCVTTIImpl::getPartialReductionCost(
+    unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
+    ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
+    TTI::PartialReductionExtendKind OpBExtend,
+    std::optional<unsigned> BinOp) const {
+
+  // zve32x is broken for partial_reduce_umla, but let's make sure we
+  // don't generate them.
+  if (!ST->hasStdExtZvqdotq() || ST->getELen() < 64 ||
+      Opcode != Instruction::Add || !BinOp || *BinOp != Instruction::Mul ||
+      InputTypeA != InputTypeB || !InputTypeA->isIntegerTy(8) ||
+      OpAExtend != OpBExtend || !AccumType->isIntegerTy(32) ||
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lukel97 wrote:

Should we add a TODO to remove the OpAExtend != OpBExtend restriction once there's a signed-unsigned SD node that we're able to lower to vqdotsu?

https://github.com/llvm/llvm-project/pull/140974