[llvm] a58e2d1 - [RISCV] Add compress patterns for qc.extu and qc.mvltui (#140682)

[via llvm-commits]

Author: quic_hchandel
Date: 2025-05-23T14:20:31+05:30
New Revision: a58e2d1393f16f032d01ae20673eb1a2211f7754

URL: https://github.com/llvm/llvm-project/commit/a58e2d1393f16f032d01ae20673eb1a2211f7754
DIFF: https://github.com/llvm/llvm-project/commit/a58e2d1393f16f032d01ae20673eb1a2211f7754.diff

LOG: [RISCV] Add compress patterns for qc.extu and qc.mvltui (#140682)

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    llvm/test/MC/RISCV/xqcibm-valid.s
    llvm/test/MC/RISCV/xqcicm-valid.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 30849f24d2660..c4d6d2d704526 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1489,6 +1489,9 @@ def : CompressPat<(QC_E_SW GPR:$rs2, GPRMem:$rs1, simm12:$imm12),
 let Predicates = [HasVendorXqcicm, IsRV32] in {
 def : CompressPat<(QC_MVEQI GPRC:$rd, GPRC:$rd, 0, GPRC:$rs1),
                   (QC_C_MVEQZ GPRC:$rd, GPRC:$rs1)>;
+let isCompressOnly = true in
+def : CompressPat<(QC_MVLTUI GPRC:$rd, GPRC:$rd, 1, GPRC:$rs1),
+                  (QC_C_MVEQZ GPRC:$rd, GPRC:$rs1)>;
 }
 
 let Predicates = [HasVendorXqcibm, IsRV32] in {
@@ -1501,6 +1504,9 @@ def : CompressPat<(BSETI GPRC:$rs1, GPRC:$rs1, uimmlog2xlennonzero:$shamt),
                   (QC_C_BSETI GPRC:$rs1, uimmlog2xlennonzero:$shamt)>;
 def : CompressPat<(BEXTI GPRC:$rs1, GPRC:$rs1, uimmlog2xlennonzero:$shamt),
                   (QC_C_BEXTI GPRC:$rs1, uimmlog2xlennonzero:$shamt)>;
+let isCompressOnly = true in
+def : CompressPat<(QC_EXTU GPRC:$rd, GPRC:$rd, 1, uimmlog2xlennonzero:$shamt),
+                  (QC_C_BEXTI GPRC:$rd, uimmlog2xlennonzero:$shamt)>;
 } // Predicates = [HasVendorXqcibm, HasStdExtZbs, IsRV32]
 
 let isCompressOnly = true, Predicates = [HasVendorXqcilb, IsRV32] in {

diff  --git a/llvm/test/MC/RISCV/xqcibm-valid.s b/llvm/test/MC/RISCV/xqcibm-valid.s
index 4bbf2bc2b01d0..090b72834364b 100644
--- a/llvm/test/MC/RISCV/xqcibm-valid.s
+++ b/llvm/test/MC/RISCV/xqcibm-valid.s
@@ -133,6 +133,11 @@ qc.c.extu x15, 32
 # CHECK-ENC: encoding: [0xaa,0x15]
 qc.extu x11, x11, 11, 0
 
+# CHECK-NOALIAS: qc.c.bexti  a1, 5
+# CHECK-ALIAS: bexti   a1, a1, 5
+# CHECK-ENC: encoding: [0x95,0x91]
+qc.extu x11, x11, 1, 5
+
 # CHECK-NOALIAS: qc.c.bexti  s1, 8
 # CHECK-ALIAS: bexti s1, s1, 8
 # CHECK-ENC-ZBS: encoding: [0xa1,0x90]

diff  --git a/llvm/test/MC/RISCV/xqcicm-valid.s b/llvm/test/MC/RISCV/xqcicm-valid.s
index f480a9e5fb007..0eb253ff5e434 100644
--- a/llvm/test/MC/RISCV/xqcicm-valid.s
+++ b/llvm/test/MC/RISCV/xqcicm-valid.s
@@ -130,3 +130,8 @@ qc.mvgeui x9, x10, 31, x12
 # CHECK-ENC: encoding: [0x06,0xae]
 qc.mveqi x9, x9, 0, x12
 
+# CHECK-NOALIAS: qc.c.mveqz s1, a2
+# CHECK-ALIAS: qc.mveqi s1, s1, 0, a2
+# CHECK-ENC: encoding: [0x06,0xae]
+qc.mvltui x9, x9, 1, x12
+