[llvm] [HVX] Support lowering of setuo, seto. (PR #140765)
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Thu May 22 21:42:10 PDT 2025
https://github.com/kaushik-quicinc updated https://github.com/llvm/llvm-project/pull/140765
>From 88b77a48ddaa81abe17c3955fd5fb80cd064de05 Mon Sep 17 00:00:00 2001
From: Kaushik Kulkarni <quic_kauskulk at quicinc.com>
Date: Tue, 20 May 2025 10:27:02 -0700
Subject: [PATCH 1/5] [HVX] Support lowering of setuo,seto.
---
.../Target/Hexagon/HexagonISelLoweringHVX.cpp | 4 ++++
llvm/test/MC/Hexagon/inst_setcc_uno_uo.ll | 20 +++++++++++++++++++
2 files changed, 24 insertions(+)
create mode 100644 llvm/test/MC/Hexagon/inst_setcc_uno_uo.ll
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index fbbcacf0d713e..af3682ab38fa1 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -349,6 +349,8 @@ HexagonTargetLowering::initializeHVXLowering() {
setCondCodeAction(ISD::SETULE, MVT::v64f16, Expand);
setCondCodeAction(ISD::SETUGE, MVT::v64f16, Expand);
setCondCodeAction(ISD::SETULT, MVT::v64f16, Expand);
+ setCondCodeAction(ISD::SETUO, MVT::v64f16, Expand);
+ setCondCodeAction(ISD::SETO, MVT::v64f16, Expand);
setCondCodeAction(ISD::SETNE, MVT::v32f32, Expand);
setCondCodeAction(ISD::SETLE, MVT::v32f32, Expand);
@@ -362,6 +364,8 @@ HexagonTargetLowering::initializeHVXLowering() {
setCondCodeAction(ISD::SETULE, MVT::v32f32, Expand);
setCondCodeAction(ISD::SETUGE, MVT::v32f32, Expand);
setCondCodeAction(ISD::SETULT, MVT::v32f32, Expand);
+ setCondCodeAction(ISD::SETUO, MVT::v32f32, Expand);
+ setCondCodeAction(ISD::SETO, MVT::v32f32, Expand);
// Boolean vectors.
diff --git a/llvm/test/MC/Hexagon/inst_setcc_uno_uo.ll b/llvm/test/MC/Hexagon/inst_setcc_uno_uo.ll
new file mode 100644
index 0000000000000..fa94f60b088c8
--- /dev/null
+++ b/llvm/test/MC/Hexagon/inst_setcc_uno_uo.ll
@@ -0,0 +1,20 @@
+;; RUN: llc -mv79 -mhvx %s -o - | FileCheck %s
+source_filename = "isnan.c"
+target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
+target triple = "hexagon"
+
+; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
+define dso_local void @foo(ptr noundef readonly captures(none) %a, ptr noundef writeonly captures(none) %isnan_a) local_unnamed_addr #0 {
+entry:
+ %arrayidx = getelementptr inbounds nuw float, ptr %a, i32 0
+ %0 = load <32 x float>, ptr %arrayidx, align 4
+ %.ripple.vectorized = fcmp uno <32 x float> %0, zeroinitializer
+ %arrayidx1 = getelementptr inbounds nuw i8, ptr %isnan_a, i32 0
+ %storedv.ripple.LS.instance = zext <32 x i1> %.ripple.vectorized to <32 x i8>
+ store <32 x i8> %storedv.ripple.LS.instance, ptr %arrayidx1, align 1
+ ret void
+}
+
+;; CHECK: vcmp.eq
+
+attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv79" "target-features"="+hmx,+hvx-length128b,+hvxv79,+v79,-long-calls" }
>From a087e112c5612a9328bc89d1bd4f34e5375e4dd5 Mon Sep 17 00:00:00 2001
From: kaushik-quicinc <quic_kauskulk at quicinc.com>
Date: Wed, 21 May 2025 17:18:38 -0700
Subject: [PATCH 2/5] Add setcc:uno, uo checks for f16
---
llvm/test/MC/Hexagon/inst_setcc_uno_uo.ll | 32 ++++++++++++++---------
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/llvm/test/MC/Hexagon/inst_setcc_uno_uo.ll b/llvm/test/MC/Hexagon/inst_setcc_uno_uo.ll
index fa94f60b088c8..eeee12e86950f 100644
--- a/llvm/test/MC/Hexagon/inst_setcc_uno_uo.ll
+++ b/llvm/test/MC/Hexagon/inst_setcc_uno_uo.ll
@@ -1,20 +1,28 @@
-;; RUN: llc -mv79 -mhvx %s -o - | FileCheck %s
-source_filename = "isnan.c"
-target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
-target triple = "hexagon"
+;; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b %s -o - | FileCheck %s
-; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite)
-define dso_local void @foo(ptr noundef readonly captures(none) %a, ptr noundef writeonly captures(none) %isnan_a) local_unnamed_addr #0 {
+define dso_local void @store_isnan_f32(ptr %a, ptr %isnan_a) local_unnamed_addr {
entry:
%arrayidx = getelementptr inbounds nuw float, ptr %a, i32 0
%0 = load <32 x float>, ptr %arrayidx, align 4
- %.ripple.vectorized = fcmp uno <32 x float> %0, zeroinitializer
- %arrayidx1 = getelementptr inbounds nuw i8, ptr %isnan_a, i32 0
- %storedv.ripple.LS.instance = zext <32 x i1> %.ripple.vectorized to <32 x i8>
- store <32 x i8> %storedv.ripple.LS.instance, ptr %arrayidx1, align 1
+ %.vectorized = fcmp uno <32 x float> %0, zeroinitializer
+ %.LS.instance = zext <32 x i1> %.vectorized to <32 x i32>
+ %arrayidx1 = getelementptr inbounds nuw i32, ptr %isnan_a, i32 0
+ store <32 x i32> %.LS.instance, ptr %arrayidx1, align 4
ret void
}
+;; CHECK: store_isnan_f32
+;; CHECK: vcmp.eq({{v[0-9]+.w}},{{v[0-9]+.w}})
-;; CHECK: vcmp.eq
+define dso_local void @store_isnan_f16(ptr %a, ptr %isnan_a) local_unnamed_addr {
+entry:
+ %arrayidx = getelementptr inbounds nuw half, ptr %a, i32 0
+ %0 = load <64 x half>, ptr %arrayidx, align 2
+ %.vectorized = fcmp uno <64 x half> %0, zeroinitializer
+ %conv.LS.instance = zext <64 x i1> %.vectorized to <64 x i16>
+ %arrayidx1 = getelementptr inbounds nuw i16, ptr %isnan_a, i32 0
+ store <64 x i16> %conv.LS.instance, ptr %arrayidx1, align 2
+ ret void
+}
-attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv79" "target-features"="+hmx,+hvx-length128b,+hvxv79,+v79,-long-calls" }
+;; CHECK: store_isnan_f16
+;; CHECK: vcmp.eq({{v[0-9]+.h}},{{v[0-9]+.h}})
>From ca8ed960a7bd58e1ba46c717a2b06ab4899e6dd8 Mon Sep 17 00:00:00 2001
From: kaushik-quicinc <quic_kauskulk at quicinc.com>
Date: Thu, 22 May 2025 11:30:03 -0700
Subject: [PATCH 3/5] Use -mcpu=hexagonv79 instead of -mhvx79
---
llvm/test/MC/Hexagon/inst_setcc_uno_uo.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/MC/Hexagon/inst_setcc_uno_uo.ll b/llvm/test/MC/Hexagon/inst_setcc_uno_uo.ll
index eeee12e86950f..81ed065a9e95f 100644
--- a/llvm/test/MC/Hexagon/inst_setcc_uno_uo.ll
+++ b/llvm/test/MC/Hexagon/inst_setcc_uno_uo.ll
@@ -1,4 +1,4 @@
-;; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b %s -o - | FileCheck %s
+;; RUN: llc --mtriple=hexagon -mcpu=hexagonv79 -mattr=+hvx,+hvx-length128b %s -o - | FileCheck %s
define dso_local void @store_isnan_f32(ptr %a, ptr %isnan_a) local_unnamed_addr {
entry:
>From e046dd8898880104d394c4bf108c544379886a3b Mon Sep 17 00:00:00 2001
From: Kaushik Kulkarni <quic_kauskulk at quicinc.com>
Date: Thu, 22 May 2025 17:30:54 -0700
Subject: [PATCH 4/5] Use mattr=hvx79
Change-Id: I576265fdbe07d1dbba5ed0a8e63c72b76ce44b32
---
llvm/test/{MC => CodeGen}/Hexagon/inst_setcc_uno_uo.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
rename llvm/test/{MC => CodeGen}/Hexagon/inst_setcc_uno_uo.ll (91%)
diff --git a/llvm/test/MC/Hexagon/inst_setcc_uno_uo.ll b/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll
similarity index 91%
rename from llvm/test/MC/Hexagon/inst_setcc_uno_uo.ll
rename to llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll
index 81ed065a9e95f..dd3811c7a53bd 100644
--- a/llvm/test/MC/Hexagon/inst_setcc_uno_uo.ll
+++ b/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll
@@ -1,4 +1,4 @@
-;; RUN: llc --mtriple=hexagon -mcpu=hexagonv79 -mattr=+hvx,+hvx-length128b %s -o - | FileCheck %s
+;; RUN: llc --mtriple=hexagon -mattr=+hvx79,+hvx-length128b %s -o - | FileCheck %s
define dso_local void @store_isnan_f32(ptr %a, ptr %isnan_a) local_unnamed_addr {
entry:
>From 42e57aea398fe6cc0dad02f40f3b02ae8d38e361 Mon Sep 17 00:00:00 2001
From: kaushik-quicinc <quic_kauskulk at quicinc.com>
Date: Thu, 22 May 2025 21:42:00 -0700
Subject: [PATCH 5/5] Fix typo. hvx79->hvxv79
---
llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll b/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll
index dd3811c7a53bd..eeee12e86950f 100644
--- a/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll
+++ b/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll
@@ -1,4 +1,4 @@
-;; RUN: llc --mtriple=hexagon -mattr=+hvx79,+hvx-length128b %s -o - | FileCheck %s
+;; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b %s -o - | FileCheck %s
define dso_local void @store_isnan_f32(ptr %a, ptr %isnan_a) local_unnamed_addr {
entry:
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