[llvm] 0635ef8 - [LoongArch][NFC] Improve csrxchg instrinsic test case (#141060)
via llvm-commits
llvm-commits at lists.llvm.org
Thu May 22 18:30:32 PDT 2025
Author: hev
Date: 2025-05-23T09:30:29+08:00
New Revision: 0635ef8240ffe493169fb353fb004df2fb20353b
URL: https://github.com/llvm/llvm-project/commit/0635ef8240ffe493169fb353fb004df2fb20353b
DIFF: https://github.com/llvm/llvm-project/commit/0635ef8240ffe493169fb353fb004df2fb20353b.diff
LOG: [LoongArch][NFC] Improve csrxchg instrinsic test case (#141060)
Took xry's idea [^1] to improve the csrxchg instrinsic test case.
[^1]:
https://github.com/llvm/llvm-project/pull/141037#issuecomment-2900955906
Added:
Modified:
llvm/test/CodeGen/LoongArch/csrxchg-intrinsic.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/LoongArch/csrxchg-intrinsic.ll b/llvm/test/CodeGen/LoongArch/csrxchg-intrinsic.ll
index 2f38b3a8c7ad1..cdeb7a008b848 100644
--- a/llvm/test/CodeGen/LoongArch/csrxchg-intrinsic.ll
+++ b/llvm/test/CodeGen/LoongArch/csrxchg-intrinsic.ll
@@ -13,12 +13,11 @@ entry:
}
;; Check that the rj operand of csrxchg is not R1.
-define i32 @csrxchg_w_rj_not_r1() {
+define i32 @csrxchg_w_rj_not_r1(i32 %0) {
; CHECK-NOT: csrxchg ${{[a-z]*}}, $r1, 0
; CHECK-NOT: csrxchg ${{[a-z]*}}, $ra, 0
entry:
- %0 = tail call i32 asm "", "=r,r,i,{r4},{r5},{r6},{r7},{r8},{r9},{r10},{r11},{r12},{r13},{r14},{r15},{r16},{r17},{r18},{r19},{r20},{r23},{r24},{r25},{r26},{r27},{r28},{r29},{r30},{r31},0"(i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
- %1 = tail call i32 @llvm.loongarch.csrxchg.w(i32 %0, i32 4, i32 0)
- %2 = tail call i32 asm "", "=r,r,i,{r4},{r5},{r6},{r7},{r8},{r9},{r10},{r11},{r12},{r13},{r14},{r15},{r16},{r17},{r18},{r19},{r20},{r23},{r24},{r25},{r26},{r27},{r28},{r29},{r30},{r31},0"(i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 %1)
- ret i32 %2
+ %2 = tail call i32 asm "", "={$r1},{$r1}"(i32 0)
+ %3 = tail call i32 @llvm.loongarch.csrxchg.w(i32 %0, i32 %2, i32 0)
+ ret i32 %3
}
More information about the llvm-commits
mailing list