[llvm] [AArch64] Convert comparisons with 1 and -1 to 0 if it is profitable (PR #141151)
via llvm-commits
llvm-commits at lists.llvm.org
Thu May 22 16:54:54 PDT 2025
https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/141151
>From 731a40924a04c36c01ac870872632ea1ffb607b0 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Tue, 20 May 2025 16:31:08 -0400
Subject: [PATCH 1/3] [AArch64] Pre-commit test (NFC)
---
llvm/test/CodeGen/AArch64/cmp-to-cmn.ll | 184 ++++++++++++++++++++++++
1 file changed, 184 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/cmp-to-cmn.ll b/llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
index e87d43161a895..6b08e4b37190e 100644
--- a/llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
+++ b/llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
@@ -430,3 +430,187 @@ entry:
%cmp = icmp ne i32 %conv, %add
ret i1 %cmp
}
+
+define i1 @cmn_large_imm(i32 %a) {
+; CHECK-LABEL: cmn_large_imm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #64765 // =0xfcfd
+; CHECK-NEXT: movk w8, #64764, lsl #16
+; CHECK-NEXT: cmp w0, w8
+; CHECK-NEXT: cset w0, gt
+; CHECK-NEXT: ret
+ %cmp = icmp sgt i32 %a, -50529027
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_slt(i32 %x) {
+; CHECK-LABEL: almost_immediate_neg_slt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #4097 // =0x1001
+; CHECK-NEXT: movk w8, #65281, lsl #16
+; CHECK-NEXT: cmp w0, w8
+; CHECK-NEXT: cset w0, lt
+; CHECK-NEXT: ret
+ %cmp = icmp slt i32 %x, -16707583
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_slt_64(i64 %x) {
+; CHECK-LABEL: almost_immediate_neg_slt_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #-61439 // =0xffffffffffff1001
+; CHECK-NEXT: movk x8, #65281, lsl #16
+; CHECK-NEXT: cmp x0, x8
+; CHECK-NEXT: cset w0, lt
+; CHECK-NEXT: ret
+ %cmp = icmp slt i64 %x, -16707583
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_sge(i32 %x) {
+; CHECK-LABEL: almost_immediate_neg_sge:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmn w0, #4079, lsl #12 // =16707584
+; CHECK-NEXT: cset w0, gt
+; CHECK-NEXT: ret
+ %cmp = icmp sge i32 %x, -16707583
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_sge_64(i64 %x) {
+; CHECK-LABEL: almost_immediate_neg_sge_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmn x0, #4079, lsl #12 // =16707584
+; CHECK-NEXT: cset w0, gt
+; CHECK-NEXT: ret
+ %cmp = icmp sge i64 %x, -16707583
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_uge(i32 %x) {
+; CHECK-LABEL: almost_immediate_neg_uge:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmn w0, #4079, lsl #12 // =16707584
+; CHECK-NEXT: cset w0, hi
+; CHECK-NEXT: ret
+ %cmp = icmp uge i32 %x, -16707583
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_uge_64(i64 %x) {
+; CHECK-LABEL: almost_immediate_neg_uge_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmn x0, #4079, lsl #12 // =16707584
+; CHECK-NEXT: cset w0, hi
+; CHECK-NEXT: ret
+ %cmp = icmp uge i64 %x, -16707583
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_ult(i32 %x) {
+; CHECK-LABEL: almost_immediate_neg_ult:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #4097 // =0x1001
+; CHECK-NEXT: movk w8, #65281, lsl #16
+; CHECK-NEXT: cmp w0, w8
+; CHECK-NEXT: cset w0, lo
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, -16707583
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_ult_64(i64 %x) {
+; CHECK-LABEL: almost_immediate_neg_ult_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #-61439 // =0xffffffffffff1001
+; CHECK-NEXT: movk x8, #65281, lsl #16
+; CHECK-NEXT: cmp x0, x8
+; CHECK-NEXT: cset w0, lo
+; CHECK-NEXT: ret
+ %cmp = icmp ult i64 %x, -16707583
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_sle(i32 %x) {
+; CHECK-LABEL: almost_immediate_neg_sle:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmn w0, #4095, lsl #12 // =16773120
+; CHECK-NEXT: cset w0, lt
+; CHECK-NEXT: ret
+ %cmp = icmp sle i32 %x, -16773121
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_sle_64(i64 %x) {
+; CHECK-LABEL: almost_immediate_neg_sle_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmn x0, #4095, lsl #12 // =16773120
+; CHECK-NEXT: cset w0, lt
+; CHECK-NEXT: ret
+ %cmp = icmp sle i64 %x, -16773121
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_sgt(i32 %x) {
+; CHECK-LABEL: almost_immediate_neg_sgt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #-16773121 // =0xff000fff
+; CHECK-NEXT: cmp w0, w8
+; CHECK-NEXT: cset w0, gt
+; CHECK-NEXT: ret
+ %cmp = icmp sgt i32 %x, -16773121
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_sgt_64(i64 %x) {
+; CHECK-LABEL: almost_immediate_neg_sgt_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #-16773121 // =0xffffffffff000fff
+; CHECK-NEXT: cmp x0, x8
+; CHECK-NEXT: cset w0, gt
+; CHECK-NEXT: ret
+ %cmp = icmp sgt i64 %x, -16773121
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_ule(i32 %x) {
+; CHECK-LABEL: almost_immediate_neg_ule:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmn w0, #4095, lsl #12 // =16773120
+; CHECK-NEXT: cset w0, lo
+; CHECK-NEXT: ret
+ %cmp = icmp ule i32 %x, -16773121
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_ule_64(i64 %x) {
+; CHECK-LABEL: almost_immediate_neg_ule_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmn x0, #4095, lsl #12 // =16773120
+; CHECK-NEXT: cset w0, lo
+; CHECK-NEXT: ret
+ %cmp = icmp ule i64 %x, -16773121
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_ugt(i32 %x) {
+; CHECK-LABEL: almost_immediate_neg_ugt:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #-16773121 // =0xff000fff
+; CHECK-NEXT: cmp w0, w8
+; CHECK-NEXT: cset w0, hi
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i32 %x, -16773121
+ ret i1 %cmp
+}
+
+define i1 @almost_immediate_neg_ugt_64(i64 %x) {
+; CHECK-LABEL: almost_immediate_neg_ugt_64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov x8, #-16773121 // =0xffffffffff000fff
+; CHECK-NEXT: cmp x0, x8
+; CHECK-NEXT: cset w0, hi
+; CHECK-NEXT: ret
+ %cmp = icmp ugt i64 %x, -16773121
+ ret i1 %cmp
+}
>From 4fff569008d0279a7358c39c27407a5240d1d208 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Wed, 21 May 2025 22:46:34 -0400
Subject: [PATCH 2/3] [AArch64] Check for immediates using isLegalICmpImmediate
We can catch negatives that can be encoded in cmn this way!
---
.../Target/AArch64/AArch64ISelLowering.cpp | 62 ++--
llvm/test/CodeGen/AArch64/arm64-csel.ll | 5 +-
.../check-sign-bit-before-extension.ll | 16 +-
llvm/test/CodeGen/AArch64/cmp-to-cmn.ll | 44 +--
.../test/CodeGen/AArch64/csel-subs-swapped.ll | 18 +-
.../test/CodeGen/AArch64/fptosi-sat-scalar.ll | 20 +-
.../test/CodeGen/AArch64/fptosi-sat-vector.ll | 10 +-
.../CodeGen/AArch64/select-constant-xor.ll | 4 +-
llvm/test/CodeGen/AArch64/signbit-shift.ll | 8 +-
llvm/test/CodeGen/AArch64/signbit-test.ll | 30 +-
llvm/test/CodeGen/AArch64/tbz-tbnz.ll | 306 ++++++++++++++----
.../CodeGen/AArch64/typepromotion-signed.ll | 8 +-
.../AArch64/use-cr-result-of-dom-icmp-st.ll | 20 +-
llvm/test/CodeGen/AArch64/win64_vararg.ll | 8 +-
14 files changed, 361 insertions(+), 198 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index b7f0bcfd015bc..e896717d4a06d 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -3647,6 +3647,16 @@ static bool isLegalArithImmed(uint64_t C) {
return IsLegal;
}
+bool isLegalCmpImmed(int64_t Immed) {
+ if (Immed == std::numeric_limits<int64_t>::min()) {
+ LLVM_DEBUG(dbgs() << "Illegal add imm " << Immed
+ << ": avoid UB for INT64_MIN\n");
+ return false;
+ }
+ // Same encoding for add/sub, just flip the sign.
+ return isLegalArithImmed((uint64_t)std::abs(Immed));
+}
+
static bool cannotBeIntMin(SDValue CheckedVal, SelectionDAG &DAG) {
KnownBits KnownSrc = DAG.computeKnownBits(CheckedVal);
return !KnownSrc.getSignedMinValue().isMinSignedValue();
@@ -4077,52 +4087,53 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
const SDLoc &dl) {
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
EVT VT = RHS.getValueType();
- uint64_t C = RHSC->getZExtValue();
- if (!isLegalArithImmed(C)) {
+ int64_t C = RHSC->getSExtValue();
+ if (!isLegalCmpImmed(C)) {
// Constant does not fit, try adjusting it by one?
switch (CC) {
default:
break;
case ISD::SETLT:
case ISD::SETGE:
- if ((VT == MVT::i32 && C != 0x80000000 &&
- isLegalArithImmed((uint32_t)(C - 1))) ||
- (VT == MVT::i64 && C != 0x80000000ULL &&
- isLegalArithImmed(C - 1ULL))) {
+ if ((VT == MVT::i32 && C != INT32_MIN && isLegalCmpImmed(C - 1)) ||
+ (VT == MVT::i64 && C != INT64_MIN && isLegalCmpImmed(C - 1))) {
CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
- C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
+ C = C - 1;
+ if (VT == MVT::i32)
+ C &= 0xFFFFFFFF;
RHS = DAG.getConstant(C, dl, VT);
}
break;
case ISD::SETULT:
case ISD::SETUGE:
- if ((VT == MVT::i32 && C != 0 &&
- isLegalArithImmed((uint32_t)(C - 1))) ||
- (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
+ if ((VT == MVT::i32 && C != 0 && isLegalCmpImmed(C - 1)) ||
+ (VT == MVT::i64 && C != 0 && isLegalCmpImmed(C - 1))) {
CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
- C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
+ C = C - 1;
+ if (VT == MVT::i32)
+ C &= 0xFFFFFFFF;
RHS = DAG.getConstant(C, dl, VT);
}
break;
case ISD::SETLE:
case ISD::SETGT:
- if ((VT == MVT::i32 && C != INT32_MAX &&
- isLegalArithImmed((uint32_t)(C + 1))) ||
- (VT == MVT::i64 && C != INT64_MAX &&
- isLegalArithImmed(C + 1ULL))) {
+ if ((VT == MVT::i32 && C != INT32_MAX && isLegalCmpImmed(C + 1)) ||
+ (VT == MVT::i64 && C != INT64_MAX && isLegalCmpImmed(C + 1))) {
CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
- C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
+ C = C + 1;
+ if (VT == MVT::i32)
+ C &= 0xFFFFFFFF;
RHS = DAG.getConstant(C, dl, VT);
}
break;
case ISD::SETULE:
case ISD::SETUGT:
- if ((VT == MVT::i32 && C != UINT32_MAX &&
- isLegalArithImmed((uint32_t)(C + 1))) ||
- (VT == MVT::i64 && C != UINT64_MAX &&
- isLegalArithImmed(C + 1ULL))) {
+ if ((VT == MVT::i32 && C != -1 && isLegalCmpImmed(C + 1)) ||
+ (VT == MVT::i64 && C != -1 && isLegalCmpImmed(C + 1))) {
CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
- C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
+ C = C + 1;
+ if (VT == MVT::i32)
+ C &= 0xFFFFFFFF;
RHS = DAG.getConstant(C, dl, VT);
}
break;
@@ -4141,7 +4152,7 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
// can be turned into:
// cmp w12, w11, lsl #1
if (!isa<ConstantSDNode>(RHS) ||
- !isLegalArithImmed(RHS->getAsAPIntVal().abs().getZExtValue())) {
+ !isLegalCmpImmed(RHS->getAsAPIntVal().getSExtValue())) {
bool LHSIsCMN = isCMN(LHS, CC, DAG);
bool RHSIsCMN = isCMN(RHS, CC, DAG);
SDValue TheLHS = LHSIsCMN ? LHS.getOperand(1) : LHS;
@@ -17673,12 +17684,7 @@ bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
return false;
}
// Same encoding for add/sub, just flip the sign.
- Immed = std::abs(Immed);
- bool IsLegal = ((Immed >> 12) == 0 ||
- ((Immed & 0xfff) == 0 && Immed >> 24 == 0));
- LLVM_DEBUG(dbgs() << "Is " << Immed
- << " legal add imm: " << (IsLegal ? "yes" : "no") << "\n");
- return IsLegal;
+ return isLegalArithImmed((uint64_t)std::abs(Immed));
}
bool AArch64TargetLowering::isLegalAddScalableImmediate(int64_t Imm) const {
diff --git a/llvm/test/CodeGen/AArch64/arm64-csel.ll b/llvm/test/CodeGen/AArch64/arm64-csel.ll
index 1cf99d1b31a8b..69fad57a683ac 100644
--- a/llvm/test/CodeGen/AArch64/arm64-csel.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-csel.ll
@@ -100,9 +100,8 @@ define i32 @foo7(i32 %a, i32 %b) nounwind {
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: cneg w9, w8, mi
; CHECK-NEXT: cmn w8, #1
-; CHECK-NEXT: csel w10, w9, w0, lt
-; CHECK-NEXT: cmp w8, #0
-; CHECK-NEXT: csel w0, w10, w9, ge
+; CHECK-NEXT: csel w8, w9, w0, lt
+; CHECK-NEXT: csel w0, w8, w9, gt
; CHECK-NEXT: ret
entry:
%sub = sub nsw i32 %a, %b
diff --git a/llvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll b/llvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll
index 8fbed8bfdb3fd..1d60929f2b94c 100644
--- a/llvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll
+++ b/llvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll
@@ -14,8 +14,8 @@ define i32 @f_i8_sign_extend_inreg(i8 %in, i32 %a, i32 %b) nounwind {
; CHECK-LABEL: f_i8_sign_extend_inreg:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sxtb w8, w0
-; CHECK-NEXT: cmp w8, #0
-; CHECK-NEXT: csel w8, w1, w2, ge
+; CHECK-NEXT: cmn w8, #1
+; CHECK-NEXT: csel w8, w1, w2, gt
; CHECK-NEXT: add w0, w8, w0, uxtb
; CHECK-NEXT: ret
entry:
@@ -36,8 +36,8 @@ define i32 @f_i16_sign_extend_inreg(i16 %in, i32 %a, i32 %b) nounwind {
; CHECK-LABEL: f_i16_sign_extend_inreg:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sxth w8, w0
-; CHECK-NEXT: cmp w8, #0
-; CHECK-NEXT: csel w8, w1, w2, ge
+; CHECK-NEXT: cmn w8, #1
+; CHECK-NEXT: csel w8, w1, w2, gt
; CHECK-NEXT: add w0, w8, w0, uxth
; CHECK-NEXT: ret
entry:
@@ -57,8 +57,8 @@ B:
define i64 @f_i32_sign_extend_inreg(i32 %in, i64 %a, i64 %b) nounwind {
; CHECK-LABEL: f_i32_sign_extend_inreg:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: cmp w0, #0
-; CHECK-NEXT: csel x8, x1, x2, ge
+; CHECK-NEXT: cmn w0, #1
+; CHECK-NEXT: csel x8, x1, x2, gt
; CHECK-NEXT: add x0, x8, w0, uxtw
; CHECK-NEXT: ret
entry:
@@ -145,8 +145,8 @@ define i64 @f_i32_sign_extend_i64(i32 %in, i64 %a, i64 %b) nounwind {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: sxtw x8, w0
-; CHECK-NEXT: cmp x8, #0
-; CHECK-NEXT: csel x8, x1, x2, ge
+; CHECK-NEXT: cmn x8, #1
+; CHECK-NEXT: csel x8, x1, x2, gt
; CHECK-NEXT: add x0, x8, w0, uxtw
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/cmp-to-cmn.ll b/llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
index 6b08e4b37190e..c5fd9b63cce97 100644
--- a/llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
+++ b/llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
@@ -446,10 +446,8 @@ define i1 @cmn_large_imm(i32 %a) {
define i1 @almost_immediate_neg_slt(i32 %x) {
; CHECK-LABEL: almost_immediate_neg_slt:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #4097 // =0x1001
-; CHECK-NEXT: movk w8, #65281, lsl #16
-; CHECK-NEXT: cmp w0, w8
-; CHECK-NEXT: cset w0, lt
+; CHECK-NEXT: cmn w0, #4079, lsl #12 // =16707584
+; CHECK-NEXT: cset w0, le
; CHECK-NEXT: ret
%cmp = icmp slt i32 %x, -16707583
ret i1 %cmp
@@ -458,10 +456,8 @@ define i1 @almost_immediate_neg_slt(i32 %x) {
define i1 @almost_immediate_neg_slt_64(i64 %x) {
; CHECK-LABEL: almost_immediate_neg_slt_64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-61439 // =0xffffffffffff1001
-; CHECK-NEXT: movk x8, #65281, lsl #16
-; CHECK-NEXT: cmp x0, x8
-; CHECK-NEXT: cset w0, lt
+; CHECK-NEXT: cmn x0, #4079, lsl #12 // =16707584
+; CHECK-NEXT: cset w0, le
; CHECK-NEXT: ret
%cmp = icmp slt i64 %x, -16707583
ret i1 %cmp
@@ -510,10 +506,8 @@ define i1 @almost_immediate_neg_uge_64(i64 %x) {
define i1 @almost_immediate_neg_ult(i32 %x) {
; CHECK-LABEL: almost_immediate_neg_ult:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #4097 // =0x1001
-; CHECK-NEXT: movk w8, #65281, lsl #16
-; CHECK-NEXT: cmp w0, w8
-; CHECK-NEXT: cset w0, lo
+; CHECK-NEXT: cmn w0, #4079, lsl #12 // =16707584
+; CHECK-NEXT: cset w0, ls
; CHECK-NEXT: ret
%cmp = icmp ult i32 %x, -16707583
ret i1 %cmp
@@ -522,10 +516,8 @@ define i1 @almost_immediate_neg_ult(i32 %x) {
define i1 @almost_immediate_neg_ult_64(i64 %x) {
; CHECK-LABEL: almost_immediate_neg_ult_64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-61439 // =0xffffffffffff1001
-; CHECK-NEXT: movk x8, #65281, lsl #16
-; CHECK-NEXT: cmp x0, x8
-; CHECK-NEXT: cset w0, lo
+; CHECK-NEXT: cmn x0, #4079, lsl #12 // =16707584
+; CHECK-NEXT: cset w0, ls
; CHECK-NEXT: ret
%cmp = icmp ult i64 %x, -16707583
ret i1 %cmp
@@ -554,9 +546,8 @@ define i1 @almost_immediate_neg_sle_64(i64 %x) {
define i1 @almost_immediate_neg_sgt(i32 %x) {
; CHECK-LABEL: almost_immediate_neg_sgt:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-16773121 // =0xff000fff
-; CHECK-NEXT: cmp w0, w8
-; CHECK-NEXT: cset w0, gt
+; CHECK-NEXT: cmn w0, #4095, lsl #12 // =16773120
+; CHECK-NEXT: cset w0, ge
; CHECK-NEXT: ret
%cmp = icmp sgt i32 %x, -16773121
ret i1 %cmp
@@ -565,9 +556,8 @@ define i1 @almost_immediate_neg_sgt(i32 %x) {
define i1 @almost_immediate_neg_sgt_64(i64 %x) {
; CHECK-LABEL: almost_immediate_neg_sgt_64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-16773121 // =0xffffffffff000fff
-; CHECK-NEXT: cmp x0, x8
-; CHECK-NEXT: cset w0, gt
+; CHECK-NEXT: cmn x0, #4095, lsl #12 // =16773120
+; CHECK-NEXT: cset w0, ge
; CHECK-NEXT: ret
%cmp = icmp sgt i64 %x, -16773121
ret i1 %cmp
@@ -596,9 +586,8 @@ define i1 @almost_immediate_neg_ule_64(i64 %x) {
define i1 @almost_immediate_neg_ugt(i32 %x) {
; CHECK-LABEL: almost_immediate_neg_ugt:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-16773121 // =0xff000fff
-; CHECK-NEXT: cmp w0, w8
-; CHECK-NEXT: cset w0, hi
+; CHECK-NEXT: cmn w0, #4095, lsl #12 // =16773120
+; CHECK-NEXT: cset w0, hs
; CHECK-NEXT: ret
%cmp = icmp ugt i32 %x, -16773121
ret i1 %cmp
@@ -607,9 +596,8 @@ define i1 @almost_immediate_neg_ugt(i32 %x) {
define i1 @almost_immediate_neg_ugt_64(i64 %x) {
; CHECK-LABEL: almost_immediate_neg_ugt_64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-16773121 // =0xffffffffff000fff
-; CHECK-NEXT: cmp x0, x8
-; CHECK-NEXT: cset w0, hi
+; CHECK-NEXT: cmn x0, #4095, lsl #12 // =16773120
+; CHECK-NEXT: cset w0, hs
; CHECK-NEXT: ret
%cmp = icmp ugt i64 %x, -16773121
ret i1 %cmp
diff --git a/llvm/test/CodeGen/AArch64/csel-subs-swapped.ll b/llvm/test/CodeGen/AArch64/csel-subs-swapped.ll
index 3971da27cdddc..7d2c7854baf3d 100644
--- a/llvm/test/CodeGen/AArch64/csel-subs-swapped.ll
+++ b/llvm/test/CodeGen/AArch64/csel-subs-swapped.ll
@@ -44,10 +44,8 @@ define i32 @sge_i32(i32 %x) {
; CHECK-LABEL: sge_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000
-; CHECK-NEXT: mov w9, #-2097153 // =0xffdfffff
-; CHECK-NEXT: sub w8, w8, w0
-; CHECK-NEXT: cmp w0, w9
-; CHECK-NEXT: csel w0, w0, w8, gt
+; CHECK-NEXT: subs w8, w8, w0
+; CHECK-NEXT: csel w0, w0, w8, le
; CHECK-NEXT: ret
%cmp = icmp sge i32 %x, -2097152
%sub = sub i32 -2097152, %x
@@ -72,10 +70,8 @@ define i32 @sle_i32(i32 %x) {
; CHECK-LABEL: sle_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000
-; CHECK-NEXT: mov w9, #-2097151 // =0xffe00001
-; CHECK-NEXT: sub w8, w8, w0
-; CHECK-NEXT: cmp w0, w9
-; CHECK-NEXT: csel w0, w0, w8, lt
+; CHECK-NEXT: subs w8, w8, w0
+; CHECK-NEXT: csel w0, w0, w8, ge
; CHECK-NEXT: ret
%cmp = icmp sle i32 %x, -2097152
%sub = sub i32 -2097152, %x
@@ -128,10 +124,8 @@ define i32 @ule_i32(i32 %x) {
; CHECK-LABEL: ule_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000
-; CHECK-NEXT: mov w9, #-2097151 // =0xffe00001
-; CHECK-NEXT: sub w8, w8, w0
-; CHECK-NEXT: cmp w0, w9
-; CHECK-NEXT: csel w0, w0, w8, lo
+; CHECK-NEXT: subs w8, w8, w0
+; CHECK-NEXT: csel w0, w0, w8, hs
; CHECK-NEXT: ret
%cmp = icmp ule i32 %x, -2097152
%sub = sub i32 -2097152, %x
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
index 39e2db3a52d2c..b766da2a3a829 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
@@ -23,8 +23,9 @@ define i1 @test_signed_i1_f32(float %f) nounwind {
; CHECK-SD-LABEL: test_signed_i1_f32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: fcvtzs w8, s0
-; CHECK-SD-NEXT: ands w8, w8, w8, asr #31
-; CHECK-SD-NEXT: csinv w8, w8, wzr, ge
+; CHECK-SD-NEXT: and w8, w8, w8, asr #31
+; CHECK-SD-NEXT: cmn w8, #1
+; CHECK-SD-NEXT: csinv w8, w8, wzr, gt
; CHECK-SD-NEXT: and w0, w8, #0x1
; CHECK-SD-NEXT: ret
;
@@ -268,8 +269,9 @@ define i1 @test_signed_i1_f64(double %f) nounwind {
; CHECK-SD-LABEL: test_signed_i1_f64:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: fcvtzs w8, d0
-; CHECK-SD-NEXT: ands w8, w8, w8, asr #31
-; CHECK-SD-NEXT: csinv w8, w8, wzr, ge
+; CHECK-SD-NEXT: and w8, w8, w8, asr #31
+; CHECK-SD-NEXT: cmn w8, #1
+; CHECK-SD-NEXT: csinv w8, w8, wzr, gt
; CHECK-SD-NEXT: and w0, w8, #0x1
; CHECK-SD-NEXT: ret
;
@@ -518,16 +520,18 @@ define i1 @test_signed_i1_f16(half %f) nounwind {
; CHECK-SD-CVT: // %bb.0:
; CHECK-SD-CVT-NEXT: fcvt s0, h0
; CHECK-SD-CVT-NEXT: fcvtzs w8, s0
-; CHECK-SD-CVT-NEXT: ands w8, w8, w8, asr #31
-; CHECK-SD-CVT-NEXT: csinv w8, w8, wzr, ge
+; CHECK-SD-CVT-NEXT: and w8, w8, w8, asr #31
+; CHECK-SD-CVT-NEXT: cmn w8, #1
+; CHECK-SD-CVT-NEXT: csinv w8, w8, wzr, gt
; CHECK-SD-CVT-NEXT: and w0, w8, #0x1
; CHECK-SD-CVT-NEXT: ret
;
; CHECK-SD-FP16-LABEL: test_signed_i1_f16:
; CHECK-SD-FP16: // %bb.0:
; CHECK-SD-FP16-NEXT: fcvtzs w8, h0
-; CHECK-SD-FP16-NEXT: ands w8, w8, w8, asr #31
-; CHECK-SD-FP16-NEXT: csinv w8, w8, wzr, ge
+; CHECK-SD-FP16-NEXT: and w8, w8, w8, asr #31
+; CHECK-SD-FP16-NEXT: cmn w8, #1
+; CHECK-SD-FP16-NEXT: csinv w8, w8, wzr, gt
; CHECK-SD-FP16-NEXT: and w0, w8, #0x1
; CHECK-SD-FP16-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index a33b1ef569fc3..3d7bcf6409438 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -2371,10 +2371,12 @@ define <2 x i1> @test_signed_v2f64_v2i1(<2 x double> %f) {
; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: fcvtzs w9, d0
; CHECK-SD-NEXT: fcvtzs w8, d1
-; CHECK-SD-NEXT: ands w8, w8, w8, asr #31
-; CHECK-SD-NEXT: csinv w8, w8, wzr, ge
-; CHECK-SD-NEXT: ands w9, w9, w9, asr #31
-; CHECK-SD-NEXT: csinv w9, w9, wzr, ge
+; CHECK-SD-NEXT: and w9, w9, w9, asr #31
+; CHECK-SD-NEXT: and w8, w8, w8, asr #31
+; CHECK-SD-NEXT: cmn w8, #1
+; CHECK-SD-NEXT: csinv w8, w8, wzr, gt
+; CHECK-SD-NEXT: cmn w9, #1
+; CHECK-SD-NEXT: csinv w9, w9, wzr, gt
; CHECK-SD-NEXT: fmov s0, w9
; CHECK-SD-NEXT: mov v0.s[1], w8
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
diff --git a/llvm/test/CodeGen/AArch64/select-constant-xor.ll b/llvm/test/CodeGen/AArch64/select-constant-xor.ll
index 6803411f66896..fe9a2c0fad830 100644
--- a/llvm/test/CodeGen/AArch64/select-constant-xor.ll
+++ b/llvm/test/CodeGen/AArch64/select-constant-xor.ll
@@ -168,8 +168,8 @@ define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; CHECK-SD-LABEL: icmpasrne:
; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmp w0, #0
-; CHECK-SD-NEXT: csel w0, w1, w2, ge
+; CHECK-SD-NEXT: cmn w0, #1
+; CHECK-SD-NEXT: csel w0, w1, w2, gt
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: icmpasrne:
diff --git a/llvm/test/CodeGen/AArch64/signbit-shift.ll b/llvm/test/CodeGen/AArch64/signbit-shift.ll
index 253ea1cab91fb..0e6da326a31f4 100644
--- a/llvm/test/CodeGen/AArch64/signbit-shift.ll
+++ b/llvm/test/CodeGen/AArch64/signbit-shift.ll
@@ -43,8 +43,8 @@ define i32 @sel_ifpos_tval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifpos_tval_bigger:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #41 // =0x29
-; CHECK-NEXT: cmp w0, #0
-; CHECK-NEXT: cinc w0, w8, ge
+; CHECK-NEXT: cmn w0, #1
+; CHECK-NEXT: cinc w0, w8, gt
; CHECK-NEXT: ret
%c = icmp sgt i32 %x, -1
%r = select i1 %c, i32 42, i32 41
@@ -91,8 +91,8 @@ define i32 @sel_ifpos_fval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifpos_fval_bigger:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #41 // =0x29
-; CHECK-NEXT: cmp w0, #0
-; CHECK-NEXT: cinc w0, w8, lt
+; CHECK-NEXT: cmn w0, #1
+; CHECK-NEXT: cinc w0, w8, le
; CHECK-NEXT: ret
%c = icmp sgt i32 %x, -1
%r = select i1 %c, i32 41, i32 42
diff --git a/llvm/test/CodeGen/AArch64/signbit-test.ll b/llvm/test/CodeGen/AArch64/signbit-test.ll
index f5eaf80cf7f8d..c74a934ee09d8 100644
--- a/llvm/test/CodeGen/AArch64/signbit-test.ll
+++ b/llvm/test/CodeGen/AArch64/signbit-test.ll
@@ -4,9 +4,9 @@
define i64 @test_clear_mask_i64_i32(i64 %x) nounwind {
; CHECK-LABEL: test_clear_mask_i64_i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #42
-; CHECK-NEXT: cmp w0, #0
-; CHECK-NEXT: csel x0, x8, x0, ge
+; CHECK-NEXT: mov w8, #42 // =0x2a
+; CHECK-NEXT: cmn w0, #1
+; CHECK-NEXT: csel x0, x8, x0, gt
; CHECK-NEXT: ret
entry:
%a = and i64 %x, 2147483648
@@ -22,7 +22,7 @@ f:
define i64 @test_set_mask_i64_i32(i64 %x) nounwind {
; CHECK-LABEL: test_set_mask_i64_i32:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: mov w8, #42 // =0x2a
; CHECK-NEXT: tst x0, #0x80000000
; CHECK-NEXT: csel x0, x8, x0, ne
; CHECK-NEXT: ret
@@ -40,7 +40,7 @@ f:
define i64 @test_clear_mask_i64_i16(i64 %x) nounwind {
; CHECK-LABEL: test_clear_mask_i64_i16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: mov w8, #42 // =0x2a
; CHECK-NEXT: tst x0, #0x8000
; CHECK-NEXT: csel x0, x8, x0, eq
; CHECK-NEXT: ret
@@ -58,7 +58,7 @@ f:
define i64 @test_set_mask_i64_i16(i64 %x) nounwind {
; CHECK-LABEL: test_set_mask_i64_i16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: mov w8, #42 // =0x2a
; CHECK-NEXT: tst x0, #0x8000
; CHECK-NEXT: csel x0, x8, x0, ne
; CHECK-NEXT: ret
@@ -76,7 +76,7 @@ f:
define i64 @test_clear_mask_i64_i8(i64 %x) nounwind {
; CHECK-LABEL: test_clear_mask_i64_i8:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: mov w8, #42 // =0x2a
; CHECK-NEXT: tst x0, #0x80
; CHECK-NEXT: csel x0, x8, x0, eq
; CHECK-NEXT: ret
@@ -94,7 +94,7 @@ f:
define i64 @test_set_mask_i64_i8(i64 %x) nounwind {
; CHECK-LABEL: test_set_mask_i64_i8:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: mov w8, #42 // =0x2a
; CHECK-NEXT: tst x0, #0x80
; CHECK-NEXT: csel x0, x8, x0, ne
; CHECK-NEXT: ret
@@ -112,7 +112,7 @@ f:
define i32 @test_clear_mask_i32_i16(i32 %x) nounwind {
; CHECK-LABEL: test_clear_mask_i32_i16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: mov w8, #42 // =0x2a
; CHECK-NEXT: tst w0, #0x8000
; CHECK-NEXT: csel w0, w8, w0, eq
; CHECK-NEXT: ret
@@ -130,7 +130,7 @@ f:
define i32 @test_set_mask_i32_i16(i32 %x) nounwind {
; CHECK-LABEL: test_set_mask_i32_i16:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: mov w8, #42 // =0x2a
; CHECK-NEXT: tst w0, #0x8000
; CHECK-NEXT: csel w0, w8, w0, ne
; CHECK-NEXT: ret
@@ -148,7 +148,7 @@ f:
define i32 @test_clear_mask_i32_i8(i32 %x) nounwind {
; CHECK-LABEL: test_clear_mask_i32_i8:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: mov w8, #42 // =0x2a
; CHECK-NEXT: tst w0, #0x80
; CHECK-NEXT: csel w0, w8, w0, eq
; CHECK-NEXT: ret
@@ -166,7 +166,7 @@ f:
define i32 @test_set_mask_i32_i8(i32 %x) nounwind {
; CHECK-LABEL: test_set_mask_i32_i8:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: mov w8, #42 // =0x2a
; CHECK-NEXT: tst w0, #0x80
; CHECK-NEXT: csel w0, w8, w0, ne
; CHECK-NEXT: ret
@@ -184,7 +184,7 @@ f:
define i16 @test_clear_mask_i16_i8(i16 %x) nounwind {
; CHECK-LABEL: test_clear_mask_i16_i8:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: mov w8, #42 // =0x2a
; CHECK-NEXT: tst w0, #0x80
; CHECK-NEXT: csel w0, w8, w0, eq
; CHECK-NEXT: ret
@@ -202,7 +202,7 @@ f:
define i16 @test_set_mask_i16_i8(i16 %x) nounwind {
; CHECK-LABEL: test_set_mask_i16_i8:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: mov w8, #42 // =0x2a
; CHECK-NEXT: tst w0, #0x80
; CHECK-NEXT: csel w0, w8, w0, ne
; CHECK-NEXT: ret
@@ -220,7 +220,7 @@ f:
define i16 @test_set_mask_i16_i7(i16 %x) nounwind {
; CHECK-LABEL: test_set_mask_i16_i7:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: mov w8, #42 // =0x2a
; CHECK-NEXT: tst w0, #0x40
; CHECK-NEXT: csel w0, w8, w0, ne
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/tbz-tbnz.ll b/llvm/test/CodeGen/AArch64/tbz-tbnz.ll
index d301a380dbb84..86a0f45030f9c 100644
--- a/llvm/test/CodeGen/AArch64/tbz-tbnz.ll
+++ b/llvm/test/CodeGen/AArch64/tbz-tbnz.ll
@@ -1,16 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -O1 -mtriple=aarch64 -aarch64-enable-cond-br-tune=false | FileCheck %s
declare void @t()
define void @test1(i32 %a) {
-; CHECK-LABEL: @test1
+; CHECK-LABEL: test1:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sub w8, w0, #12
+; CHECK-NEXT: tbnz w8, #31, .LBB0_2
+; CHECK-NEXT: // %bb.1: // %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB0_2: // %if.then
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl t
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
entry:
%sub = add nsw i32 %a, -12
%cmp = icmp slt i32 %sub, 0
br i1 %cmp, label %if.then, label %if.end
-; CHECK: sub [[CMP:w[0-9]+]], w0, #12
-; CHECK: tbnz [[CMP]], #31
if.then:
call void @t()
@@ -21,14 +32,24 @@ if.end:
}
define void @test2(i64 %a) {
-; CHECK-LABEL: @test2
+; CHECK-LABEL: test2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sub x8, x0, #12
+; CHECK-NEXT: tbnz x8, #63, .LBB1_2
+; CHECK-NEXT: // %bb.1: // %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB1_2: // %if.then
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl t
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
entry:
%sub = add nsw i64 %a, -12
%cmp = icmp slt i64 %sub, 0
br i1 %cmp, label %if.then, label %if.end
-; CHECK: sub [[CMP:x[0-9]+]], x0, #12
-; CHECK: tbnz [[CMP]], #63
if.then:
call void @t()
@@ -39,14 +60,23 @@ if.end:
}
define void @test3(i32 %a) {
-; CHECK-LABEL: @test3
+; CHECK-LABEL: test3:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sub w8, w0, #12
+; CHECK-NEXT: tbnz w8, #31, .LBB2_2
+; CHECK-NEXT: // %bb.1: // %if.then
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl t
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: .LBB2_2: // %if.end
+; CHECK-NEXT: ret
entry:
%sub = add nsw i32 %a, -12
%cmp = icmp sgt i32 %sub, -1
br i1 %cmp, label %if.then, label %if.end
-; CHECK: sub [[CMP:w[0-9]+]], w0, #12
-; CHECK: tbnz [[CMP]], #31
if.then:
call void @t()
@@ -57,14 +87,23 @@ if.end:
}
define void @test4(i64 %a) {
-; CHECK-LABEL: @test4
+; CHECK-LABEL: test4:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sub x8, x0, #12
+; CHECK-NEXT: tbnz x8, #63, .LBB3_2
+; CHECK-NEXT: // %bb.1: // %if.then
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl t
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: .LBB3_2: // %if.end
+; CHECK-NEXT: ret
entry:
%sub = add nsw i64 %a, -12
%cmp = icmp sgt i64 %sub, -1
br i1 %cmp, label %if.then, label %if.end
-; CHECK: sub [[CMP:x[0-9]+]], x0, #12
-; CHECK: tbnz [[CMP]], #63
if.then:
call void @t()
@@ -75,14 +114,23 @@ if.end:
}
define void @test5(i32 %a) {
-; CHECK-LABEL: @test5
+; CHECK-LABEL: test5:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sub w8, w0, #12
+; CHECK-NEXT: tbnz w8, #31, .LBB4_2
+; CHECK-NEXT: // %bb.1: // %if.then
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl t
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: .LBB4_2: // %if.end
+; CHECK-NEXT: ret
entry:
%sub = add nsw i32 %a, -12
%cmp = icmp sge i32 %sub, 0
br i1 %cmp, label %if.then, label %if.end
-; CHECK: sub [[CMP:w[0-9]+]], w0, #12
-; CHECK: tbnz [[CMP]], #31
if.then:
call void @t()
@@ -93,14 +141,23 @@ if.end:
}
define void @test6(i64 %a) {
-; CHECK-LABEL: @test6
+; CHECK-LABEL: test6:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sub x8, x0, #12
+; CHECK-NEXT: tbnz x8, #63, .LBB5_2
+; CHECK-NEXT: // %bb.1: // %if.then
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl t
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: .LBB5_2: // %if.end
+; CHECK-NEXT: ret
entry:
%sub = add nsw i64 %a, -12
%cmp = icmp sge i64 %sub, 0
br i1 %cmp, label %if.then, label %if.end
-; CHECK: sub [[CMP:x[0-9]+]], x0, #12
-; CHECK: tbnz [[CMP]], #63
if.then:
call void @t()
@@ -111,14 +168,24 @@ if.end:
}
define void @test7(i32 %a) {
-; CHECK-LABEL: @test7
+; CHECK-LABEL: test7:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sub w8, w0, #12
+; CHECK-NEXT: tbnz w8, #31, .LBB6_2
+; CHECK-NEXT: // %bb.1: // %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB6_2: // %if.then
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl t
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
entry:
%sub = sub nsw i32 %a, 12
%cmp = icmp slt i32 %sub, 0
br i1 %cmp, label %if.then, label %if.end
-; CHECK: sub [[CMP:w[0-9]+]], w0, #12
-; CHECK: tbnz [[CMP]], #31
if.then:
call void @t()
@@ -129,22 +196,40 @@ if.end:
}
define void @test8(i64 %val1, i64 %val2, i64 %val3) {
-; CHECK-LABEL: @test8
+; CHECK-LABEL: test8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and x8, x0, x1
+; CHECK-NEXT: cmn x8, #1
+; CHECK-NEXT: b.gt .LBB7_3
+; CHECK-NEXT: // %bb.1:
+; CHECK-NEXT: and x8, x1, x2
+; CHECK-NEXT: tbnz x8, #63, .LBB7_3
+; CHECK-NEXT: // %bb.2: // %if.then2
+; CHECK-NEXT: and x8, x0, x1, lsl #63
+; CHECK-NEXT: cmn x8, #1
+; CHECK-NEXT: b.le .LBB7_4
+; CHECK-NEXT: .LBB7_3: // %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB7_4: // %if.then3
+; CHECK-NEXT: tst x0, x1, lsl #62
+; CHECK-NEXT: b.lt .LBB7_3
+; CHECK-NEXT: // %bb.5: // %if.then4
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl t
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
%and1 = and i64 %val1, %val2
%tst1 = icmp slt i64 %and1, 0
br i1 %tst1, label %if.then1, label %if.end
-; CHECK: tst x0, x1
-; CHECK-NEXT: b.ge
if.then1:
%and2 = and i64 %val2, %val3
%tst2 = icmp sge i64 %and2, 0
br i1 %tst2, label %if.then2, label %if.end
-; CHECK: and [[CMP:x[0-9]+]], x1, x2
-; CHECK-NOT: cmp
-; CHECK: tbnz [[CMP]], #63
if.then2:
%shifted_op1 = shl i64 %val2, 63
@@ -152,8 +237,6 @@ if.then2:
%tst3 = icmp slt i64 %shifted_and1, 0
br i1 %tst3, label %if.then3, label %if.end
-; CHECK: tst x0, x1, lsl #63
-; CHECK: b.lt
if.then3:
%shifted_op2 = shl i64 %val2, 62
@@ -161,8 +244,6 @@ if.then3:
%tst4 = icmp sge i64 %shifted_and2, 0
br i1 %tst4, label %if.then4, label %if.end
-; CHECK: tst x0, x1, lsl #62
-; CHECK: b.lt
if.then4:
call void @t()
@@ -173,12 +254,21 @@ if.end:
}
define void @test9(i64 %val1) {
-; CHECK-LABEL: @test9
+; CHECK-LABEL: test9:
+; CHECK: // %bb.0:
+; CHECK-NEXT: tbnz x0, #63, .LBB8_2
+; CHECK-NEXT: // %bb.1: // %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB8_2: // %if.then
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl t
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
%tst = icmp slt i64 %val1, 0
br i1 %tst, label %if.then, label %if.end
-; CHECK-NOT: cmp
-; CHECK: tbnz x0, #63
if.then:
call void @t()
@@ -189,12 +279,21 @@ if.end:
}
define void @test10(i64 %val1) {
-; CHECK-LABEL: @test10
+; CHECK-LABEL: test10:
+; CHECK: // %bb.0:
+; CHECK-NEXT: tbnz x0, #63, .LBB9_2
+; CHECK-NEXT: // %bb.1: // %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB9_2: // %if.then
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl t
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
%tst = icmp slt i64 %val1, 0
br i1 %tst, label %if.then, label %if.end
-; CHECK-NOT: cmp
-; CHECK: tbnz x0, #63
if.then:
call void @t()
@@ -205,11 +304,20 @@ if.end:
}
define void @test11(i64 %val1, ptr %ptr) {
-; CHECK-LABEL: @test11
+; CHECK-LABEL: test11:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr x8, [x1]
+; CHECK-NEXT: tbnz x8, #63, .LBB10_2
+; CHECK-NEXT: // %bb.1: // %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB10_2: // %if.then
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl t
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
-; CHECK: ldr [[CMP:x[0-9]+]], [x1]
-; CHECK-NOT: cmp
-; CHECK: tbnz [[CMP]], #63
%val = load i64, ptr %ptr
%tst = icmp slt i64 %val, 0
@@ -224,12 +332,21 @@ if.end:
}
define void @test12(i64 %val1) {
-; CHECK-LABEL: @test12
+; CHECK-LABEL: test12:
+; CHECK: // %bb.0:
+; CHECK-NEXT: tbnz x0, #63, .LBB11_2
+; CHECK-NEXT: // %bb.1: // %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB11_2: // %if.then
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl t
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
%tst = icmp slt i64 %val1, 0
br i1 %tst, label %if.then, label %if.end
-; CHECK-NOT: cmp
-; CHECK: tbnz x0, #63
if.then:
call void @t()
@@ -240,14 +357,23 @@ if.end:
}
define void @test13(i64 %val1, i64 %val2) {
-; CHECK-LABEL: @test13
+; CHECK-LABEL: test13:
+; CHECK: // %bb.0:
+; CHECK-NEXT: orr x8, x0, x1
+; CHECK-NEXT: tbnz x8, #63, .LBB12_2
+; CHECK-NEXT: // %bb.1: // %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB12_2: // %if.then
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl t
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: ret
%or = or i64 %val1, %val2
%tst = icmp slt i64 %or, 0
br i1 %tst, label %if.then, label %if.end
-; CHECK: orr [[CMP:x[0-9]+]], x0, x1
-; CHECK-NOT: cmp
-; CHECK: tbnz [[CMP]], #63
if.then:
call void @t()
@@ -258,11 +384,19 @@ if.end:
}
define void @test14(i1 %cond) {
-; CHECK-LABEL: @test14
+; CHECK-LABEL: test14:
+; CHECK: // %bb.0:
+; CHECK-NEXT: tbnz w0, #0, .LBB13_2
+; CHECK-NEXT: // %bb.1: // %if.then
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl t
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: .LBB13_2: // %if.end
+; CHECK-NEXT: ret
br i1 %cond, label %if.end, label %if.then
-; CHECK-NOT: and
-; CHECK: tbnz w0, #0
if.then:
call void @t()
@@ -273,12 +407,20 @@ if.end:
}
define void @test15(i1 %cond) {
-; CHECK-LABEL: @test15
+; CHECK-LABEL: test15:
+; CHECK: // %bb.0:
+; CHECK-NEXT: tbnz w0, #0, .LBB14_2
+; CHECK-NEXT: // %bb.1: // %if.then
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl t
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: .LBB14_2: // %if.end
+; CHECK-NEXT: ret
%cond1 = xor i1 %cond, -1
br i1 %cond1, label %if.then, label %if.end
-; CHECK-NOT: movn
-; CHECK: tbnz w0, #0
if.then:
call void @t()
@@ -289,14 +431,22 @@ if.end:
}
define void @test16(i64 %in) {
-; CHECK-LABEL: @test16
+; CHECK-LABEL: test16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: tbnz w0, #2, .LBB15_2
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl t
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: .LBB15_2: // %end
+; CHECK-NEXT: ret
%shl = shl i64 %in, 3
%and = and i64 %shl, 32
%cond = icmp eq i64 %and, 0
br i1 %cond, label %then, label %end
-; CHECK-NOT: lsl
-; CHECK: tbnz w0, #2
then:
call void @t()
@@ -307,14 +457,22 @@ end:
}
define void @test17(i64 %in) {
-; CHECK-LABEL: @test17
+; CHECK-LABEL: test17:
+; CHECK: // %bb.0:
+; CHECK-NEXT: tbnz w0, #3, .LBB16_2
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl t
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: .LBB16_2: // %end
+; CHECK-NEXT: ret
%shr = ashr i64 %in, 3
%and = and i64 %shr, 1
%cond = icmp eq i64 %and, 0
br i1 %cond, label %then, label %end
-; CHECK-NOT: lsr
-; CHECK: tbnz w0, #3
then:
call void @t()
@@ -325,13 +483,21 @@ end:
}
define void @test18(i32 %in) {
-; CHECK-LABEL: @test18
+; CHECK-LABEL: test18:
+; CHECK: // %bb.0:
+; CHECK-NEXT: tbnz w0, #31, .LBB17_2
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl t
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: .LBB17_2: // %end
+; CHECK-NEXT: ret
%shr = ashr i32 %in, 2
%cond = icmp sge i32 %shr, 0
br i1 %cond, label %then, label %end
-; CHECK-NOT: asr
-; CHECK: tbnz w0, #31
then:
call void @t()
@@ -342,15 +508,23 @@ end:
}
define void @test19(i64 %in) {
-; CHECK-LABEL: @test19
+; CHECK-LABEL: test19:
+; CHECK: // %bb.0:
+; CHECK-NEXT: tbnz w0, #3, .LBB18_2
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: bl t
+; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; CHECK-NEXT: .LBB18_2: // %end
+; CHECK-NEXT: ret
%shl = lshr i64 %in, 3
%trunc = trunc i64 %shl to i32
%and = and i32 %trunc, 1
%cond = icmp eq i32 %and, 0
br i1 %cond, label %then, label %end
-; CHECK-NOT: ubfx
-; CHECK: tbnz w0, #3
then:
call void @t()
diff --git a/llvm/test/CodeGen/AArch64/typepromotion-signed.ll b/llvm/test/CodeGen/AArch64/typepromotion-signed.ll
index 212f02d86850b..0feac24062647 100644
--- a/llvm/test/CodeGen/AArch64/typepromotion-signed.ll
+++ b/llvm/test/CodeGen/AArch64/typepromotion-signed.ll
@@ -60,9 +60,9 @@ define i32 @test_signext_b(ptr nocapture readonly %ptr, i8 signext %arg) {
; CHECK-NEXT: mov w8, #20894 // =0x519e
; CHECK-NEXT: add w9, w9, w1
; CHECK-NEXT: sxtb w9, w9
-; CHECK-NEXT: cmp w9, #0
+; CHECK-NEXT: cmn w9, #1
; CHECK-NEXT: mov w9, #42 // =0x2a
-; CHECK-NEXT: csel w0, w9, w8, ge
+; CHECK-NEXT: csel w0, w9, w8, gt
; CHECK-NEXT: ret
entry:
%0 = load i8, ptr %ptr, align 1
@@ -100,9 +100,9 @@ define i32 @test_signext_h(ptr nocapture readonly %ptr, i16 signext %arg) {
; CHECK-NEXT: mov w8, #20894 // =0x519e
; CHECK-NEXT: add w9, w9, w1
; CHECK-NEXT: sxth w9, w9
-; CHECK-NEXT: cmp w9, #0
+; CHECK-NEXT: cmn w9, #1
; CHECK-NEXT: mov w9, #42 // =0x2a
-; CHECK-NEXT: csel w0, w9, w8, ge
+; CHECK-NEXT: csel w0, w9, w8, gt
; CHECK-NEXT: ret
entry:
%0 = load i16, ptr %ptr, align 1
diff --git a/llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll b/llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll
index d23e23c752350..f475b384b67e0 100644
--- a/llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll
+++ b/llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll
@@ -43,10 +43,9 @@ define i64 @ll_a_op_b__1(i64 %a, i64 %b) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl x8, x0, x1
; CHECK-NEXT: cmn x8, #1
-; CHECK-NEXT: csinc x9, x1, xzr, eq
-; CHECK-NEXT: cmp x8, #0
-; CHECK-NEXT: mul x9, x9, x0
-; CHECK-NEXT: csel x0, x1, x9, ge
+; CHECK-NEXT: csinc x8, x1, xzr, eq
+; CHECK-NEXT: mul x8, x8, x0
+; CHECK-NEXT: csel x0, x1, x8, gt
; CHECK-NEXT: ret
entry:
%shl = shl i64 %a, %b
@@ -162,9 +161,8 @@ define i64 @ll_a__1(i64 %a, i64 %b) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmn x0, #1
; CHECK-NEXT: csinc x8, x1, xzr, eq
-; CHECK-NEXT: cmp x0, #0
; CHECK-NEXT: mul x8, x8, x0
-; CHECK-NEXT: csel x0, x1, x8, ge
+; CHECK-NEXT: csel x0, x1, x8, gt
; CHECK-NEXT: ret
entry:
%cmp = icmp sgt i64 %a, -1
@@ -278,10 +276,9 @@ define i64 @i_a_op_b__1(i32 signext %a, i32 signext %b) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl w8, w0, w1
; CHECK-NEXT: cmn w8, #1
-; CHECK-NEXT: csinc w9, w1, wzr, eq
-; CHECK-NEXT: cmp w8, #0
-; CHECK-NEXT: mul w9, w9, w0
-; CHECK-NEXT: csel w8, w1, w9, ge
+; CHECK-NEXT: csinc w8, w1, wzr, eq
+; CHECK-NEXT: mul w8, w8, w0
+; CHECK-NEXT: csel w8, w1, w8, gt
; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret
entry:
@@ -412,9 +409,8 @@ define i64 @i_a__1(i32 signext %a, i32 signext %b) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmn w0, #1
; CHECK-NEXT: csinc w8, w1, wzr, eq
-; CHECK-NEXT: cmp w0, #0
; CHECK-NEXT: mul w8, w8, w0
-; CHECK-NEXT: csel w8, w1, w8, ge
+; CHECK-NEXT: csel w8, w1, w8, gt
; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/win64_vararg.ll b/llvm/test/CodeGen/AArch64/win64_vararg.ll
index aaf4cad608740..d72dee9021251 100644
--- a/llvm/test/CodeGen/AArch64/win64_vararg.ll
+++ b/llvm/test/CodeGen/AArch64/win64_vararg.ll
@@ -133,8 +133,8 @@ define i32 @fp(ptr, i64, ptr, ...) local_unnamed_addr #6 {
; CHECK-NEXT: mov x4, xzr
; CHECK-NEXT: orr x0, x8, #0x2
; CHECK-NEXT: bl __stdio_common_vsprintf
-; CHECK-NEXT: cmp w0, #0
-; CHECK-NEXT: csinv w0, w0, wzr, ge
+; CHECK-NEXT: cmn w0, #1
+; CHECK-NEXT: csinv w0, w0, wzr, gt
; CHECK-NEXT: .seh_startepilogue
; CHECK-NEXT: ldp x29, x30, [sp, #24] // 16-byte Folded Reload
; CHECK-NEXT: .seh_save_fplr 24
@@ -268,8 +268,8 @@ define i32 @snprintf(ptr, i64, ptr, ...) local_unnamed_addr #5 {
; CHECK-NEXT: mov x4, xzr
; CHECK-NEXT: orr x0, x8, #0x2
; CHECK-NEXT: bl __stdio_common_vsprintf
-; CHECK-NEXT: cmp w0, #0
-; CHECK-NEXT: csinv w0, w0, wzr, ge
+; CHECK-NEXT: cmn w0, #1
+; CHECK-NEXT: csinv w0, w0, wzr, gt
; CHECK-NEXT: .seh_startepilogue
; CHECK-NEXT: ldp x21, x30, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: .seh_save_lrpair x21, 32
>From 89c6bff4cde8568563eb7ed682b01b70e57686d8 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Thu, 22 May 2025 17:53:59 -0400
Subject: [PATCH 3/3] [AArch64] Convert comparisons with 1 and -1 to 0 if it is
profitable
Use tst and ands!
Fixes: https://github.com/llvm/llvm-project/issues/141137
---
.../Target/AArch64/AArch64ISelLowering.cpp | 28 ++++++++++++++++++-
.../test/CodeGen/AArch64/fptosi-sat-scalar.ll | 20 ++++++-------
.../test/CodeGen/AArch64/fptosi-sat-vector.ll | 10 +++----
.../CodeGen/AArch64/logical_shifted_reg.ll | 5 ++--
llvm/test/CodeGen/AArch64/tbz-tbnz.ll | 10 +++----
5 files changed, 45 insertions(+), 28 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index e896717d4a06d..4e542960a7ba5 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -4082,13 +4082,39 @@ static unsigned getCmpOperandFoldingProfit(SDValue Op) {
return 0;
}
+// emitComparison() converts comparison with one or negative one to comparison
+// with 0.
+static bool shouldBeAdjustedToZero(SDValue LHS, int64_t C, ISD::CondCode CC) {
+ // Only works for not signed values.
+ if (isUnsignedIntSetCC(CC))
+ return false;
+ // Only works for ANDS and AND.
+ if (LHS.getOpcode() != ISD::AND && LHS.getOpcode() != AArch64ISD::ANDS)
+ return false;
+ if (C == 1 && (CC == ISD::SETLT || CC == ISD::SETGE))
+ return true;
+ if (C == -1 && (CC == ISD::SETLE || CC == ISD::SETGT))
+ return true;
+
+ return false;
+}
+
static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
SDValue &AArch64cc, SelectionDAG &DAG,
const SDLoc &dl) {
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
EVT VT = RHS.getValueType();
int64_t C = RHSC->getSExtValue();
- if (!isLegalCmpImmed(C)) {
+ // This is a special case for ands with cmn 1 so that emitComparison can
+ if (shouldBeAdjustedToZero(LHS, C, CC)) {
+ if (C == 1) {
+ CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
+ } else {
+ // C is -1
+ CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
+ }
+ RHS = DAG.getConstant(0, dl, VT);
+ } else if (!isLegalCmpImmed(C)) {
// Constant does not fit, try adjusting it by one?
switch (CC) {
default:
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
index b766da2a3a829..39e2db3a52d2c 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
@@ -23,9 +23,8 @@ define i1 @test_signed_i1_f32(float %f) nounwind {
; CHECK-SD-LABEL: test_signed_i1_f32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: fcvtzs w8, s0
-; CHECK-SD-NEXT: and w8, w8, w8, asr #31
-; CHECK-SD-NEXT: cmn w8, #1
-; CHECK-SD-NEXT: csinv w8, w8, wzr, gt
+; CHECK-SD-NEXT: ands w8, w8, w8, asr #31
+; CHECK-SD-NEXT: csinv w8, w8, wzr, ge
; CHECK-SD-NEXT: and w0, w8, #0x1
; CHECK-SD-NEXT: ret
;
@@ -269,9 +268,8 @@ define i1 @test_signed_i1_f64(double %f) nounwind {
; CHECK-SD-LABEL: test_signed_i1_f64:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: fcvtzs w8, d0
-; CHECK-SD-NEXT: and w8, w8, w8, asr #31
-; CHECK-SD-NEXT: cmn w8, #1
-; CHECK-SD-NEXT: csinv w8, w8, wzr, gt
+; CHECK-SD-NEXT: ands w8, w8, w8, asr #31
+; CHECK-SD-NEXT: csinv w8, w8, wzr, ge
; CHECK-SD-NEXT: and w0, w8, #0x1
; CHECK-SD-NEXT: ret
;
@@ -520,18 +518,16 @@ define i1 @test_signed_i1_f16(half %f) nounwind {
; CHECK-SD-CVT: // %bb.0:
; CHECK-SD-CVT-NEXT: fcvt s0, h0
; CHECK-SD-CVT-NEXT: fcvtzs w8, s0
-; CHECK-SD-CVT-NEXT: and w8, w8, w8, asr #31
-; CHECK-SD-CVT-NEXT: cmn w8, #1
-; CHECK-SD-CVT-NEXT: csinv w8, w8, wzr, gt
+; CHECK-SD-CVT-NEXT: ands w8, w8, w8, asr #31
+; CHECK-SD-CVT-NEXT: csinv w8, w8, wzr, ge
; CHECK-SD-CVT-NEXT: and w0, w8, #0x1
; CHECK-SD-CVT-NEXT: ret
;
; CHECK-SD-FP16-LABEL: test_signed_i1_f16:
; CHECK-SD-FP16: // %bb.0:
; CHECK-SD-FP16-NEXT: fcvtzs w8, h0
-; CHECK-SD-FP16-NEXT: and w8, w8, w8, asr #31
-; CHECK-SD-FP16-NEXT: cmn w8, #1
-; CHECK-SD-FP16-NEXT: csinv w8, w8, wzr, gt
+; CHECK-SD-FP16-NEXT: ands w8, w8, w8, asr #31
+; CHECK-SD-FP16-NEXT: csinv w8, w8, wzr, ge
; CHECK-SD-FP16-NEXT: and w0, w8, #0x1
; CHECK-SD-FP16-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index 3d7bcf6409438..a33b1ef569fc3 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -2371,12 +2371,10 @@ define <2 x i1> @test_signed_v2f64_v2i1(<2 x double> %f) {
; CHECK-SD-NEXT: mov d1, v0.d[1]
; CHECK-SD-NEXT: fcvtzs w9, d0
; CHECK-SD-NEXT: fcvtzs w8, d1
-; CHECK-SD-NEXT: and w9, w9, w9, asr #31
-; CHECK-SD-NEXT: and w8, w8, w8, asr #31
-; CHECK-SD-NEXT: cmn w8, #1
-; CHECK-SD-NEXT: csinv w8, w8, wzr, gt
-; CHECK-SD-NEXT: cmn w9, #1
-; CHECK-SD-NEXT: csinv w9, w9, wzr, gt
+; CHECK-SD-NEXT: ands w8, w8, w8, asr #31
+; CHECK-SD-NEXT: csinv w8, w8, wzr, ge
+; CHECK-SD-NEXT: ands w9, w9, w9, asr #31
+; CHECK-SD-NEXT: csinv w9, w9, wzr, ge
; CHECK-SD-NEXT: fmov s0, w9
; CHECK-SD-NEXT: mov v0.s[1], w8
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
diff --git a/llvm/test/CodeGen/AArch64/logical_shifted_reg.ll b/llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
index c8c1e9007c7a0..9912c7ae19493 100644
--- a/llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
+++ b/llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
@@ -257,9 +257,8 @@ define void @flag_setting() {
; CHECK-NEXT: tst x9, x10, lsl #63
; CHECK-NEXT: b.lt .LBB2_4
; CHECK-NEXT: // %bb.2: // %test3
-; CHECK-NEXT: and x10, x9, x10, asr #12
-; CHECK-NEXT: cmp x10, #1
-; CHECK-NEXT: b.ge .LBB2_4
+; CHECK-NEXT: tst x9, x10, asr #12
+; CHECK-NEXT: b.gt .LBB2_4
; CHECK-NEXT: // %bb.3: // %other_exit
; CHECK-NEXT: str x9, [x8]
; CHECK-NEXT: .LBB2_4: // %common.ret
diff --git a/llvm/test/CodeGen/AArch64/tbz-tbnz.ll b/llvm/test/CodeGen/AArch64/tbz-tbnz.ll
index 86a0f45030f9c..b3a480ebc1c68 100644
--- a/llvm/test/CodeGen/AArch64/tbz-tbnz.ll
+++ b/llvm/test/CodeGen/AArch64/tbz-tbnz.ll
@@ -198,16 +198,14 @@ if.end:
define void @test8(i64 %val1, i64 %val2, i64 %val3) {
; CHECK-LABEL: test8:
; CHECK: // %bb.0:
-; CHECK-NEXT: and x8, x0, x1
-; CHECK-NEXT: cmn x8, #1
-; CHECK-NEXT: b.gt .LBB7_3
+; CHECK-NEXT: tst x0, x1
+; CHECK-NEXT: b.ge .LBB7_3
; CHECK-NEXT: // %bb.1:
; CHECK-NEXT: and x8, x1, x2
; CHECK-NEXT: tbnz x8, #63, .LBB7_3
; CHECK-NEXT: // %bb.2: // %if.then2
-; CHECK-NEXT: and x8, x0, x1, lsl #63
-; CHECK-NEXT: cmn x8, #1
-; CHECK-NEXT: b.le .LBB7_4
+; CHECK-NEXT: tst x0, x1, lsl #63
+; CHECK-NEXT: b.lt .LBB7_4
; CHECK-NEXT: .LBB7_3: // %if.end
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB7_4: // %if.then3
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